testsuite/synth: add tests for #1537

3 files changed, 37 insertions, 0 deletions

diff --git a/testsuite/synth/issue1537/ent1.vhdl b/testsuite/synth/issue1537/ent1.vhdl
new file mode 100644
index 000000000..4a0f8433d
--- /dev/null
+++ b/testsuite/synth/issue1537/ent1.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+    port (
+        o: out std_ulogic
+    );
+end entity;
+
+architecture arch of ent1 is
+begin
+    o <= to_X01(std_ulogic' ('H'));
+end architecture;
diff --git a/testsuite/synth/issue1537/ent2.vhdl b/testsuite/synth/issue1537/ent2.vhdl
new file mode 100644
index 000000000..795b09b86
--- /dev/null
+++ b/testsuite/synth/issue1537/ent2.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        o: out std_ulogic_vector(8 downto 0)
+    );
+end entity;
+
+architecture arch of ent is
+begin
+    o <= to_X01(std_ulogic_vector'("U01XZLHW-"));
+end architecture;
diff --git a/testsuite/synth/issue1537/testsuite.sh b/testsuite/synth/issue1537/testsuite.sh
new file mode 100755
index 000000000..a7846d914
--- /dev/null
+++ b/testsuite/synth/issue1537/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in ent1 ent2 ; do
+  synth_analyze $f
+done
+
+clean
+
+echo "Test successful"