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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-25 08:16:43 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-25 20:57:33 +0100 |
| commit | 9443cb4d447460f592b645c6bc66f73bbee87c1e (patch) | |
| tree | 20f42d57107db9457b7c19098cd3dc0692f0bfdb /testsuite | |
| parent | c92813bb456ffc4d7cadee441397d22742f89fc6 (diff) | |
| download | ghdl-9443cb4d447460f592b645c6bc66f73bbee87c1e.tar.gz ghdl-9443cb4d447460f592b645c6bc66f73bbee87c1e.tar.bz2 ghdl-9443cb4d447460f592b645c6bc66f73bbee87c1e.zip | |
testsuite/synth: adjust reproducer for #2062
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/synth/issue2062/repro.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/issue2062/repro.vhdl b/testsuite/synth/issue2062/repro.vhdl index 2b676415c..9fb8694fa 100644 --- a/testsuite/synth/issue2062/repro.vhdl +++ b/testsuite/synth/issue2062/repro.vhdl @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; entity repro is port ( a : in std_logic_vector(5 downto 0); - y : out std_ulogic_vector(3 downto -2)); + y : out std_ulogic_vector(7 downto 2)); end entity; architecture beh of repro is |