testsuite/synth: add a test for #1780

3 files changed, 120 insertions, 0 deletions

diff --git a/testsuite/synth/issue1780/imem.vhdl b/testsuite/synth/issue1780/imem.vhdl
new file mode 100644
index 000000000..57848484e
--- /dev/null
+++ b/testsuite/synth/issue1780/imem.vhdl
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem is
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    ben_i  : in  std_ulogic_vector(03 downto 0);
+    addr_i : in  std_ulogic_vector(31 downto 0);
+    data_i : in  std_ulogic_vector(31 downto 0);
+    data_o : out std_ulogic_vector(31 downto 0);
+    ack_o  : out std_ulogic
+  );
+end entity;
+
+architecture imem_rtl of imem is
+
+  signal addr : std_ulogic_vector(15 downto 0);
+
+  type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+
+begin
+
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+
+  verbose: block
+  begin
+
+    process(clk_i)
+      variable memory : ram_t;
+    begin
+      if rising_edge(clk_i) then
+        if wren_i then
+          for x in 0 to 3 loop
+            if ben_i(x) then
+              memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+            end if;
+          end loop;
+        end if;
+      end if;
+    end process;
+
+    process(clk_i)
+      variable memory : ram_t;
+    begin
+      if rising_edge(clk_i) then
+        if rden_i then
+          data_o <= memory(to_integer(unsigned(addr)));
+        end if;
+      end if;
+    end process;
+  end block;
+
+end architecture;
diff --git a/testsuite/synth/issue1780/imem2.vhdl b/testsuite/synth/issue1780/imem2.vhdl
new file mode 100644
index 000000000..093b85c52
--- /dev/null
+++ b/testsuite/synth/issue1780/imem2.vhdl
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem2 is
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    ben_i  : in  std_ulogic_vector(03 downto 0);
+    addr_i : in  std_ulogic_vector(31 downto 0);
+    data_i : in  std_ulogic_vector(31 downto 0);
+    data_o : out std_ulogic_vector(31 downto 0)
+  );
+end entity;
+
+architecture imem_rtl of imem2 is
+
+  signal addr : std_ulogic_vector(7 downto 0);
+
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(31 downto 0);
+
+begin
+
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+
+  verbose: block
+  begin
+
+    process(clk_i)
+      variable memory : ram_t;
+    begin
+      if rising_edge(clk_i) then
+        if wren_i then
+          for x in 0 to 3 loop
+            if ben_i(x) then
+              memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+            end if;
+          end loop;
+        end if;
+      end if;
+    end process;
+
+    process(clk_i)
+      variable memory : ram_t;
+    begin
+      if rising_edge(clk_i) then
+        if rden_i then
+          data_o <= memory(to_integer(unsigned(addr)));
+        end if;
+      end if;
+    end process;
+  end block;
+
+end architecture;
diff --git a/testsuite/synth/issue1780/testsuite.sh b/testsuite/synth/issue1780/testsuite.sh
new file mode 100755
index 000000000..10657834f
--- /dev/null
+++ b/testsuite/synth/issue1780/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+synth_only imem2
+
+echo "Test successful"