testsuite/gna: add a test for #1528

8 files changed, 226 insertions, 0 deletions

diff --git a/testsuite/gna/issue1528/attrs_pkg.vhdl b/testsuite/gna/issue1528/attrs_pkg.vhdl
new file mode 100644
index 000000000..cc52fc745
--- /dev/null
+++ b/testsuite/gna/issue1528/attrs_pkg.vhdl
@@ -0,0 +1,11 @@
+package attrs_pkg is
+
+  attribute ent_name: string;
+  attribute ent_type: string;
+  attribute ent_stat: integer;
+
+  attribute arc_name: string;
+  attribute arc_type: string;
+  attribute arc_stat: integer;
+
+end package;
diff --git a/testsuite/gna/issue1528/ent1.vhdl b/testsuite/gna/issue1528/ent1.vhdl
new file mode 100644
index 000000000..33acefe46
--- /dev/null
+++ b/testsuite/gna/issue1528/ent1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.attrs_pkg.all;
+
+entity ent1 is
+  attribute ent_name of ent1: entity is "entity ent1";
+  attribute ent_type of ent1: entity is "LogicI";
+  attribute ent_stat of ent1: entity is 95;
+end entity ent1;
+
+architecture rtl of ent1 is
+  attribute arc_name of rtl: architecture is "rtl of ent1";
+  attribute arc_type of rtl: architecture is "RTL";
+  attribute arc_stat of rtl: architecture is 100;
+begin
+  process
+  begin
+    report "I am: " & rtl'arc_name;
+    report "Type: " & rtl'arc_type;
+    report "Status: " & integer'image(rtl'arc_stat);
+    wait;
+  end process;
+end rtl;
diff --git a/testsuite/gna/issue1528/ent2.vhdl b/testsuite/gna/issue1528/ent2.vhdl
new file mode 100644
index 000000000..66bcebfe3
--- /dev/null
+++ b/testsuite/gna/issue1528/ent2.vhdl
@@ -0,0 +1,21 @@
+use work.attrs_pkg.all;
+
+entity ent2 is
+  attribute ent_name of ent2: entity is "entity ent2";
+attribute ent_type of ent2: entity is "LogicII";
+attribute ent_stat of ent2: entity is 75;
+end entity ent2;
+
+architecture bhv of ent2 is
+attribute arc_name of bhv: architecture is "bhv of ent2";
+attribute arc_type of bhv: architecture is "BHV";
+attribute arc_stat of bhv: architecture is 100;
+begin
+process
+begin
+report "I am: " & bhv'arc_name;
+report "Type: " & bhv'arc_type;
+report "Status: " & integer'image(bhv'arc_stat);
+wait;
+end process;
+end bhv;
diff --git a/testsuite/gna/issue1528/ent3.vhdl b/testsuite/gna/issue1528/ent3.vhdl
new file mode 100644
index 000000000..460a1ed11
--- /dev/null
+++ b/testsuite/gna/issue1528/ent3.vhdl
@@ -0,0 +1,21 @@
+use work.attrs_pkg.all;
+
+entity ent3 is
+  attribute ent_name of ent3: entity is "entity ent3";
+  attribute ent_type of ent3: entity is "LogicIII";
+  attribute ent_stat of ent3: entity is 45;
+end entity ent3;
+
+architecture rtl of ent3 is
+  attribute arc_name of rtl: architecture is "rtl of ent3";
+  attribute arc_type of rtl: architecture is "RTL";
+  attribute arc_stat of rtl: architecture is 35;
+begin
+  process
+  begin
+    report "I am: " & rtl'arc_name;
+    report "Type: " & rtl'arc_type;
+    report "Status: " & integer'image(rtl'arc_stat);
+    wait;
+  end process;
+end rtl;
diff --git a/testsuite/gna/issue1528/ent4.vhdl b/testsuite/gna/issue1528/ent4.vhdl
new file mode 100644
index 000000000..1474c81af
--- /dev/null
+++ b/testsuite/gna/issue1528/ent4.vhdl
@@ -0,0 +1,15 @@
+use work.attrs_pkg.all;
+
+entity ent4 is
+  generic (name : string := "ent4 name");
+  attribute ent_name of ent4: entity is name;
+end entity;
+
+architecture rtl of ent4 is
+begin
+  process
+  begin
+    report "I am: " & ent4'ent_name;
+    wait;
+  end process;
+end rtl;
diff --git a/testsuite/gna/issue1528/testsuite.sh b/testsuite/gna/issue1528/testsuite.sh
new file mode 100755
index 000000000..7c739f917
--- /dev/null
+++ b/testsuite/gna/issue1528/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze attrs_pkg.vhdl ent1.vhdl ent2.vhdl ent3.vhdl uattr3.vhdl
+elab_simulate uattr3
+
+analyze ent4.vhdl
+analyze_failure uattr4.vhdl
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue1528/uattr3.vhdl b/testsuite/gna/issue1528/uattr3.vhdl
new file mode 100644
index 000000000..75a2ddd91
--- /dev/null
+++ b/testsuite/gna/issue1528/uattr3.vhdl
@@ -0,0 +1,113 @@
+use work.all;
+--use work.attrs_pkg.all;
+
+entity uattr3 is
+  attribute ename: string;
+  attribute ename of uattr3: entity is "user attributes 3";
+  attribute special: boolean;
+  attribute is_clock: boolean;
+  attribute sign_bit: integer;
+begin
+end entity uattr3;
+
+
+architecture tb of uattr3 is
+
+  attribute ename of tb: architecture is uattr3'ename & " Demonstration";
+  attribute stype: integer;
+
+  signal bv : bit_vector(7 downto 0) := "11000100";
+  attribute stype of bv: signal is 2;
+  attribute sign_bit of bv: signal is bv'left;
+  signal b : bit;
+  attribute stype of b: signal is 1;
+  attribute special of b: signal is true;
+  signal clk : bit;
+  attribute is_clock of clk: signal is true;
+  signal clk1 : bit;
+  signal clk2 : bit;
+
+  signal cnt : integer := 0;
+
+begin
+
+  start_up: process
+  begin
+--report "Object: " & tb'ename & " ... starting up ...";
+    wait;
+  end process start_up;
+
+  bv <= "00001111" when cnt = 0 else
+        "00011110" when cnt = 1 else
+        "00111100" when cnt = 2 else
+        "01111000" when cnt = 3 else
+        "11110000" when cnt = 4;
+
+  b <= '1' when bv = "00111100" else '0';
+
+  clock: process
+  begin
+    while cnt < 6 loop
+      wait for 1 ns;
+      clk <= not clk;
+    end loop;
+    wait;
+  end process clock;
+
+  proc1: process
+  begin
+    if(clk'event and clk = '1' and clk'is_clock) then
+      cnt <= cnt + 1;
+      clk1 <= not clk1;
+      report "Tick ... " & integer'image(cnt);
+    end if;
+
+    wait on clk;
+  end process;
+
+  bmon: process(b)
+  begin
+--report "stype of b is: " & integer'image(b'stype);
+    if b = '1' and b'special then
+--report "stype of bv is: " & integer'image(bv'stype);
+      assert bv = "00111100" report "Error: got unexpected bv value" severity failure;
+    end if;
+  end process;
+
+  bvmon: process(bv)
+    variable i_v : integer;
+    attribute stype of i_v: variable is 0;
+  begin
+    i_v := cnt;
+    case bv is
+      when "00001111" =>
+        report ent1'ent_name;
+        report ent1'ent_type;
+        report "Completeness: " & integer'image(ent1'ent_stat);
+        assert cnt = 0 report "Error0: got unexpected cnt value" severity failure;
+      when "00011110" =>
+        assert cnt = 1 report "Error1: got unexpected cnt value" severity failure;
+      when "00111100" =>
+        report ent2'ent_name;
+        report ent2'ent_type;
+        report "Completeness: " & integer'image(ent2'ent_stat);
+        assert cnt = 2 report "Error2: got unexpected cnt value" severity failure;
+      when "01111000" =>
+        assert cnt = 3 report "Error3: got unexpected cnt value" severity failure;
+      when "11110000" =>
+        report ent3'ent_name;
+        report ent3'ent_type;
+        report "Completeness: " & integer'image(ent3'ent_stat);
+        assert cnt = 4 report "Error4: got unexpected cnt value" severity failure;
+      when others =>
+--report "stype of i_v is: " & integer'image(i_v'stype);
+        null;
+    end case;
+
+  end process;
+
+  d1: entity work.ent1(rtl);
+  d2: entity work.ent2(bhv);
+  d3: entity work.ent3(rtl);
+
+end tb;
diff --git a/testsuite/gna/issue1528/uattr4.vhdl b/testsuite/gna/issue1528/uattr4.vhdl
new file mode 100644
index 000000000..19f195425
--- /dev/null
+++ b/testsuite/gna/issue1528/uattr4.vhdl
@@ -0,0 +1,8 @@
+entity uattr4 is
+end;
+
+architecture behav of uattr4 is
+begin
+  --  Not possible.
+  assert false report "ent4'ent_name = " & work.ent4'ent_name severity note;
+end behav;