testsuite/synth: add test for #1096

3 files changed, 61 insertions, 0 deletions

diff --git a/testsuite/synth/issue1096/my_entity.vhdl b/testsuite/synth/issue1096/my_entity.vhdl
new file mode 100644
index 000000000..39e236412
--- /dev/null
+++ b/testsuite/synth/issue1096/my_entity.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package mask_pkg is
+  constant MASK: std_logic_vector(0 downto 0);
+end package;
+
+package body mask_pkg is
+  constant MASK: std_logic_vector(0 downto 0) := "0";
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity my_entity is
+  port (
+    data: out std_logic_vector(0 downto 0)
+  );
+end entity;
+
+use work.mask_pkg.all;
+
+architecture arch of my_entity is
+begin
+  data <= MASK;
+end architecture;
diff --git a/testsuite/synth/issue1096/tb_my_entity.vhdl b/testsuite/synth/issue1096/tb_my_entity.vhdl
new file mode 100644
index 000000000..a63949309
--- /dev/null
+++ b/testsuite/synth/issue1096/tb_my_entity.vhdl
@@ -0,0 +1,19 @@
+entity tb_my_entity is
+end tb_my_entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_my_entity is
+  signal a : std_logic_vector(0 downto 0);
+begin
+  dut: entity work.my_entity
+    port map (a);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a = "0" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1096/testsuite.sh b/testsuite/synth/issue1096/testsuite.sh
new file mode 100755
index 000000000..2335d0b5e
--- /dev/null
+++ b/testsuite/synth/issue1096/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in my_entity; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"