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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-29 14:43:00 +0200 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-07-01 06:39:46 +0200 |
| commit | 7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7 (patch) | |
| tree | daab40c0705985c4b9f723183dfaee90fbaa14e0 /testsuite | |
| parent | 520f541c3a476bd91e0506c5fa9a3c5eaca5a842 (diff) | |
| download | ghdl-7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7.tar.gz ghdl-7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7.tar.bz2 ghdl-7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7.zip | |
Renamed '[sS]ubType' to '[sS]ubtype'.
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 4ac967c15..b2c7aff11 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -107,6 +107,14 @@ package package_1 is clk : std ); end component; + + constant Pointer_1 : List := new List(1 to 1); + constant Pointer_2 : List := new List'(1 => 0); + signal init : std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); + constant fid : real := +val; + constant ceq11 : std_logic := '1' ?= '1'; + type rt321 is range t3'reverse_range; + type rt321 is range t3'reverse_range(1); end package; package body package_1 is @@ -120,3 +128,7 @@ package body package_1 is F = 1000 mF; end units; end package body; + +vunit vu (component_1) { + +} |