synth: add support for constants.

Close #815

3 files changed, 49 insertions, 0 deletions

diff --git a/testsuite/synth/dff01/dff09.vhdl b/testsuite/synth/dff01/dff09.vhdl
new file mode 100644
index 000000000..9dcf4065a
--- /dev/null
+++ b/testsuite/synth/dff01/dff09.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff09 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic;
+        rstn : std_logic);
+end dff09;
+
+architecture behav of dff09 is
+begin
+  process (clk, rstn) is
+    constant rval : std_logic := '0';
+  begin
+    if rstn = '0' then
+      q <= rval;
+    elsif rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/dff10.vhdl b/testsuite/synth/dff01/dff10.vhdl
new file mode 100644
index 000000000..86af44865
--- /dev/null
+++ b/testsuite/synth/dff01/dff10.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff10 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        rst : std_logic;
+        en : std_logic);
+end dff10;
+
+architecture behav of dff10 is
+begin
+  process (clk) is
+    constant rval : std_logic_vector(7 downto 0) := x"55";
+  begin
+    if rst = '1' then
+      q <= rval;
+    elsif rising_edge (clk) then
+      if en = '1' then
+        q <= d;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
index 216c2dbce..a41248549 100755
--- a/testsuite/synth/dff01/testsuite.sh
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -10,6 +10,8 @@ synth dff05.vhdl -e dff05
 synth dff06.vhdl -e dff06
 synth dff07.vhdl -e dff07
 synth dff08.vhdl -e dff08
+synth dff09.vhdl -e dff09
+synth dff10.vhdl -e dff10
 
 clean