testsuite/synth: add a test for #2399

2 files changed, 129 insertions, 0 deletions

diff --git a/testsuite/synth/issue2399/repro.vhdl b/testsuite/synth/issue2399/repro.vhdl
new file mode 100644
index 000000000..ca8f8e0ee
--- /dev/null
+++ b/testsuite/synth/issue2399/repro.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub_cons is
+  generic (L : natural);
+  port (i : std_logic_vector(L-1 downto 0);
+        o : out std_logic);
+end sub_cons;
+
+architecture behav of sub_cons is
+begin
+  o <= '1' when i = (L - 1 downto 0 => '1') else '0';
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub_unsc is
+  generic (L : natural);
+  port (i : std_logic_vector;
+        o : out std_logic);
+end sub_unsc;
+
+architecture behav of sub_unsc is
+begin
+  o <= '1' when i = (i'range => '1') else '0';
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b, c: in std_logic;
+        oc : out std_logic;
+        ou : out std_logic);
+end repro;
+
+architecture behav of repro is
+begin
+  instc: entity work.sub_cons
+    generic map (L => 3)
+    port map (i(0) => a,
+              i(1) => b,
+              i(2) => c,
+              o => oc);
+
+  instu: entity work.sub_unsc
+    generic map (L => 3)
+    port map (i(0) => a,
+              i(1) => b,
+              i(2) => c,
+              o => ou);
+end behav;
diff --git a/testsuite/synth/issue2399/testsuite.sh b/testsuite/synth/issue2399/testsuite.sh
new file mode 100755
index 000000000..14485b76b
--- /dev/null
+++ b/testsuite/synth/issue2399/testsuite.sh
@@ -0,0 +1,76 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro
+
+exit 0
+
+synth --std=08                                                                 \
+  --work=fpga_cores third_party/fpga_cores/src/common_pkg.vhd                  \
+                    third_party/fpga_cores/src/interface_types_pkg.vhd         \
+                    third_party/fpga_cores/src/synchronizer.vhd                \
+                    third_party/fpga_cores/src/axi_pkg.vhd                     \
+                    third_party/fpga_cores/src/axi_stream_debug.vhd            \
+                    third_party/fpga_cores/src/axi_stream_frame_slicer.vhd     \
+                    third_party/fpga_cores/src/axi_stream_frame_padder.vhd     \
+                    third_party/fpga_cores/src/sr_delay.vhd                    \
+                    third_party/fpga_cores/src/skidbuffer.vhd                  \
+                    third_party/fpga_cores/src/ram_inference_dport.vhd         \
+                    third_party/fpga_cores/src/ram_inference.vhd               \
+                    third_party/fpga_cores/src/rom_inference.vhd               \
+                    third_party/fpga_cores/src/pipeline_context_ram.vhd        \
+                    third_party/fpga_cores/src/edge_detector.vhd               \
+                    third_party/fpga_cores/src/pulse_sync.vhd                  \
+                    third_party/fpga_cores/src/axi_stream_delay.vhd            \
+                    third_party/fpga_cores/src/sync_fifo.vhd                   \
+                    third_party/fpga_cores/src/axi_stream_credit.vhd           \
+                    third_party/fpga_cores/src/axi_stream_ram.vhd              \
+                    third_party/fpga_cores/src/axi_stream_master_adapter.vhd   \
+                    third_party/fpga_cores/src/axi_stream_flow_control.vhd     \
+                    third_party/fpga_cores/src/axi_stream_replicate.vhd        \
+                    third_party/fpga_cores/src/axi_stream_fifo.vhd             \
+                    third_party/fpga_cores/src/axi_stream_frame_fifo.vhd       \
+                    third_party/fpga_cores/src/async_fifo.vhd                  \
+                    third_party/fpga_cores/src/axi_stream_width_converter.vhd  \
+                    third_party/fpga_cores/src/axi_stream_mux.vhd              \
+                    third_party/fpga_cores/src/axi_stream_demux.vhd            \
+                    third_party/fpga_cores/src/axi_stream_arbiter.vhd          \
+  --work=work       third_party/airhdl/dvbs2_encoder_regs_pkg.vhd              \
+                    third_party/airhdl/dvbs2_encoder_regs.vhd                  \
+                    third_party/bch_generated/bch_128x64.vhd                   \
+                    third_party/bch_generated/bch_192x64.vhd                   \
+                    third_party/bch_generated/bch_128x32.vhd                   \
+                    third_party/bch_generated/bch_160x16.vhd                   \
+                    third_party/bch_generated/bch_128x16.vhd                   \
+                    third_party/bch_generated/bch_168x8.vhd                    \
+                    third_party/bch_generated/bch_192x32.vhd                   \
+                    third_party/bch_generated/bch_192x8.vhd                    \
+                    third_party/bch_generated/bch_128x8.vhd                    \
+                    third_party/bch_generated/bch_160x32.vhd                   \
+                    third_party/bch_generated/bch_160x64.vhd                   \
+                    third_party/bch_generated/bch_192x16.vhd                   \
+                    third_party/bch_generated/bch_160x8.vhd                    \
+                    rtl/axi_baseband_scrambler.vhd                             \
+                    rtl/axi_bit_interleaver.vhd                                \
+                    rtl/axi_constellation_mapper.vhd                           \
+                    rtl/axi_physical_layer_framer.vhd                          \
+                    rtl/axi_physical_layer_scrambler.vhd                       \
+                    rtl/axi_bbframe_length_enforcer.vhd                        \
+                    rtl/dvb_utils_pkg.vhd                                      \
+                    rtl/constellation_mapper_pkg.vhd                           \
+                    rtl/bch_encoder_mux.vhd                                    \
+                    rtl/axi_ldpc_table.vhd                                     \
+                    rtl/ldpc/ldpc_input_sync.vhd                               \
+                    rtl/axi_ldpc_encoder_core.vhd                              \
+                    rtl/axi_ldpc_encoder.vhd                                   \
+                    rtl/axi_plframe_header.vhd                                 \
+                    rtl/dummy_frame_generator.vhd                              \
+                    rtl/plframe_header_pkg.vhd                                 \
+                    rtl/ldpc/ldpc_pkg.vhd                                      \
+                    rtl/ldpc/ldpc_tables_pkg.vhd                               \
+                    rtl/dvbs2_encoder.vhd                                      \
+                    rtl/axi_bch_encoder.vhd                                    \
+  -e dvbs2_encoder
+
+echo "Test successful"