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authorTristan Gingold <tgingold@free.fr>2022-06-09 07:53:34 +0200
committerTristan Gingold <tgingold@free.fr>2022-06-09 07:53:34 +0200
commit634b0991bd2709fc19eec5d0af0f46a52341b70c (patch)
tree62b896d68ddfb86ac3db0c753d757cf7ff0ca9a0 /testsuite
parent46bd0ff2b72f47fa7e12612f66bcae0cb2003b7a (diff)
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testsuite/synth: add a test for #2085
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue2085/bug.vhdl27
-rwxr-xr-xtestsuite/synth/issue2085/testsuite.sh8
2 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/issue2085/bug.vhdl b/testsuite/synth/issue2085/bug.vhdl
new file mode 100644
index 000000000..0b719a075
--- /dev/null
+++ b/testsuite/synth/issue2085/bug.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+ port (
+ clk : in std_ulogic;
+ src : in std_ulogic_vector(15 downto 0);
+ dst : out std_ulogic_vector(16 downto 0)
+ );
+end bug;
+
+architecture rtl of bug is
+begin
+
+process(clk)
+ function fun(val : std_ulogic_vector) return std_ulogic_vector is
+ variable tmp : val'subtype; --this causes the crash
+ begin
+ return val;
+ end function;
+begin
+ if rising_edge(clk) then
+ dst <= '0' & fun(src);
+ end if;
+end process;
+
+end architecture;
diff --git a/testsuite/synth/issue2085/testsuite.sh b/testsuite/synth/issue2085/testsuite.sh
new file mode 100755
index 000000000..c355095b7
--- /dev/null
+++ b/testsuite/synth/issue2085/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only bug
+
+echo "Test successful"