testsuite/synth: add case for #1116

4 files changed, 97 insertions, 0 deletions

diff --git a/testsuite/synth/issue1116/ent1.vhdl b/testsuite/synth/issue1116/ent1.vhdl
new file mode 100644
index 000000000..e7621b06c
--- /dev/null
+++ b/testsuite/synth/issue1116/ent1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+	port (
+		clk : in std_logic;
+		i : in std_logic_vector(31 downto 0);
+		o : out std_logic_vector(7 downto 0)
+	);
+end;
+
+architecture a of ent1 is
+	function switch_endianness(x : std_logic_vector(31 downto 0)) return std_logic_vector is
+	begin
+		return x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24);
+	end function;
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			o <= switch_endianness(i)(7 downto 0);
+		end if;
+	end process;
+end;
diff --git a/testsuite/synth/issue1116/ent1_disp.vhdl b/testsuite/synth/issue1116/ent1_disp.vhdl
new file mode 100644
index 000000000..d031b8ec9
--- /dev/null
+++ b/testsuite/synth/issue1116/ent1_disp.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1_disp is
+	port (
+		clk : in std_logic;
+		i : in std_logic_vector(31 downto 0);
+		o : out std_logic_vector(7 downto 0)
+	);
+end;
+
+architecture a of ent1_disp is
+	function switch_endianness(x : std_logic_vector(31 downto 0)) return std_logic_vector is
+	begin
+		return x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24);
+	end function;
+
+        procedure disp (v : std_logic_vector) is
+        begin
+          report "left: " & natural'image (v'left);
+          if v'ascending then
+            report "to";
+          else
+            report "downto";
+          end if;
+          report "right: " & natural'image (v'right);
+        end disp;
+begin
+	process
+	begin
+          disp (switch_endianness(i));
+          wait;
+	end process;
+end;
diff --git a/testsuite/synth/issue1116/ent2.vhdl b/testsuite/synth/issue1116/ent2.vhdl
new file mode 100644
index 000000000..fbec42d6b
--- /dev/null
+++ b/testsuite/synth/issue1116/ent2.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+	port (
+		clk : in std_logic;
+		i : in std_logic_vector(31 downto 0);
+		o : out std_logic_vector(7 downto 0)
+	);
+end;
+
+architecture a of ent2 is
+  subtype word is std_logic_vector(31 downto 0);
+
+  function switch_endianness(x : word) return word is
+  begin
+    return x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24);
+  end function;
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			o <= switch_endianness(i)(7 downto 0);
+		end if;
+	end process;
+end;
diff --git a/testsuite/synth/issue1116/testsuite.sh b/testsuite/synth/issue1116/testsuite.sh
new file mode 100755
index 000000000..166e4c704
--- /dev/null
+++ b/testsuite/synth/issue1116/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --expect-failure ent1.vhdl -e
+
+for t in ent2; do
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"