testsuite/synth: add tests for #2077

7 files changed, 268 insertions, 0 deletions

diff --git a/testsuite/synth/issue2077/ent2.vhdl b/testsuite/synth/issue2077/ent2.vhdl
new file mode 100644
index 000000000..f4f91f827
--- /dev/null
+++ b/testsuite/synth/issue2077/ent2.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent2 is
+	generic (
+		DEPTH : positive := 256;
+		WAYS : positive := 4
+	);
+	port (
+		clk: in std_logic;
+
+		write_enable: in std_logic;
+		active_way: in natural range 0 to WAYS-1;
+		write_address: in natural range 0 to DEPTH-1;
+		input: in std_logic;
+
+		read_address: in natural range 0 to DEPTH-1;
+		outputs: out std_logic
+	);
+end entity;
+
+architecture a of ent2 is
+begin
+	process(clk)
+          type memory_t is array(0 to DEPTH-1) of std_logic;
+          type memories_t is array(0 to WAYS-1) of memory_t;
+
+          variable memories : memories_t;
+	begin
+          if rising_edge(clk) then
+            outputs <= memories(active_way)(read_address);
+
+            if write_enable then
+              memories(active_way)(write_address) := input;
+            end if;
+          end if;
+	end process;
+end architecture;
diff --git a/testsuite/synth/issue2077/ent3.vhdl b/testsuite/synth/issue2077/ent3.vhdl
new file mode 100644
index 000000000..815945dee
--- /dev/null
+++ b/testsuite/synth/issue2077/ent3.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent3 is
+	generic (
+		DEPTH : positive := 256;
+		WAYS : positive := 4
+	);
+	port (
+		clk: in std_logic;
+
+		write_enable: in std_logic;
+		active_way: in natural range 0 to WAYS-1;
+		write_address: in natural range 0 to DEPTH-1;
+		input: in std_logic;
+
+		read_address: in natural range 0 to DEPTH-1;
+		outputs: out std_logic
+	);
+end entity;
+
+architecture a of ent3 is
+begin
+	process(clk)
+--          type memory_t is array(0 to DEPTH-1) of std_logic;
+          type memories_t is array(0 to WAYS-1, 0 to DEPTH-1) of std_logic;
+
+          variable memories : memories_t;
+	begin
+          if rising_edge(clk) then
+            outputs <= memories(active_way, read_address);
+
+            if write_enable then
+              memories(active_way, write_address) := input;
+            end if;
+          end if;
+	end process;
+end architecture;
diff --git a/testsuite/synth/issue2077/ent5.vhdl b/testsuite/synth/issue2077/ent5.vhdl
new file mode 100644
index 000000000..c00deb0a8
--- /dev/null
+++ b/testsuite/synth/issue2077/ent5.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent5 is
+	generic (
+		WIDTH : positive := 8;
+		DEPTH : positive := 256;
+
+		WAYS : positive := 4
+	);
+	port (
+		clk: in std_logic;
+
+		write_enable: in std_logic;
+		active_way: in natural range 0 to WAYS-1;
+		write_address: in natural range 0 to DEPTH-1;
+		input: in std_logic_vector(WIDTH-1 downto 0);
+
+		read_address: in natural range 0 to DEPTH-1;
+		output: out std_logic_vector(WIDTH-1 downto 0)
+	);
+end entity;
+
+architecture a of ent5 is
+begin
+  process(clk)
+    type memory_t is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
+    type memories_t is array(0 to WAYS-1) of memory_t;
+
+    variable memories : memories_t;
+  begin
+    if rising_edge(clk) then
+      output <= memories(active_way)(read_address);
+
+      if write_enable then
+        memories(active_way)(write_address) := input;
+      end if;
+    end if;
+  end process;
+end architecture;
diff --git a/testsuite/synth/issue2077/tb_ent2.vhdl b/testsuite/synth/issue2077/tb_ent2.vhdl
new file mode 100644
index 000000000..667e3cf5e
--- /dev/null
+++ b/testsuite/synth/issue2077/tb_ent2.vhdl
@@ -0,0 +1,46 @@
+entity tb_ent2 is
+end tb_ent2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent2 is
+  signal addr1 : natural range 0 to 3;
+  signal waddr2, raddr2 : natural range 0 to 255;
+  signal rdat : std_logic;
+  signal wdat : std_logic;
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ent2
+    port map (clk => clk, write_enable => wen, active_way => addr1,
+              write_address => waddr2, input => wdat,
+              read_address => raddr2, outputs => rdat);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr1 <= 1;
+    waddr2 <= 3;
+    wdat <= '1';
+    wen <= '1';
+    pulse;
+
+    waddr2 <= 2;
+    wdat <= '0';
+    pulse;
+
+    raddr2 <= 3;
+    wen <= '0';
+    pulse;
+    assert rdat = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2077/tb_ent3.vhdl b/testsuite/synth/issue2077/tb_ent3.vhdl
new file mode 100644
index 000000000..6354cc39b
--- /dev/null
+++ b/testsuite/synth/issue2077/tb_ent3.vhdl
@@ -0,0 +1,46 @@
+entity tb_ent3 is
+end tb_ent3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent3 is
+  signal addr1 : natural range 0 to 3;
+  signal waddr2, raddr2 : natural range 0 to 255;
+  signal rdat : std_logic;
+  signal wdat : std_logic;
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ent3
+    port map (clk => clk, write_enable => wen, active_way => addr1,
+              write_address => waddr2, input => wdat,
+              read_address => raddr2, outputs => rdat);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr1 <= 1;
+    waddr2 <= 3;
+    wdat <= '1';
+    wen <= '1';
+    pulse;
+
+    waddr2 <= 2;
+    wdat <= '0';
+    pulse;
+
+    raddr2 <= 3;
+    wen <= '0';
+    pulse;
+    assert rdat = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2077/tb_ent5.vhdl b/testsuite/synth/issue2077/tb_ent5.vhdl
new file mode 100644
index 000000000..a55f9efd7
--- /dev/null
+++ b/testsuite/synth/issue2077/tb_ent5.vhdl
@@ -0,0 +1,46 @@
+entity tb_ent5 is
+end tb_ent5;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent5 is
+  signal addr1 : natural range 0 to 3;
+  signal waddr2, raddr2 : natural range 0 to 255;
+  signal rdat, wdat : std_logic_vector (7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ent5
+    generic map (WIDTH => 8)
+    port map (clk => clk, write_enable => wen, active_way => addr1,
+              write_address => waddr2, input => wdat,
+              read_address => raddr2, output => rdat);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr1 <= 1;
+    waddr2 <= 3;
+    wdat <= x"13";
+    wen <= '1';
+    pulse;
+
+    waddr2 <= 2;
+    wdat <= x"12";
+    pulse;
+
+    raddr2 <= 3;
+    wen <= '0';
+    pulse;
+    assert rdat = x"13" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2077/testsuite.sh b/testsuite/synth/issue2077/testsuite.sh
new file mode 100755
index 000000000..7153ca35f
--- /dev/null
+++ b/testsuite/synth/issue2077/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in ent2 ent3 ent5; do
+    synth_tb $t
+done
+
+echo "Test successful"