testsuite/synth: add a test for #1889

3 files changed, 42 insertions, 0 deletions

diff --git a/testsuite/synth/issue1889/shiftmux2.psl b/testsuite/synth/issue1889/shiftmux2.psl
new file mode 100644
index 000000000..bd9c76ec7
--- /dev/null
+++ b/testsuite/synth/issue1889/shiftmux2.psl
@@ -0,0 +1,12 @@
+vunit i_t1(shiftMux2(rtl))
+{
+   -- set all declarations to run on clk
+   default clock is rising_edge(clk);
+
+   --it breaks on this line:
+   sequence s1 is {inputA }; 
+   sequence s2 is {outputB };
+   assert always (s1) |=> (s2);
+   --this works:
+   --assert always {inputA } |=> {outputB};
+}
diff --git a/testsuite/synth/issue1889/shiftmux2.vhdl b/testsuite/synth/issue1889/shiftmux2.vhdl
new file mode 100644
index 000000000..619469500
--- /dev/null
+++ b/testsuite/synth/issue1889/shiftmux2.vhdl
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity shiftMux2 is
+  Port (
+    clk : in  std_logic;
+    --inputA
+    inputA : in std_logic;
+    outputB : out std_logic
+  );
+end shiftMux2;
+
+architecture Rtl of shiftMux2 is
+begin
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      outputB <= inputA;
+    end if;
+  end process;
+end Rtl;
diff --git a/testsuite/synth/issue1889/testsuite.sh b/testsuite/synth/issue1889/testsuite.sh
new file mode 100755
index 000000000..ad3ff5d8c
--- /dev/null
+++ b/testsuite/synth/issue1889/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth shiftmux2.vhdl shiftmux2.psl -e > syn_shiftmux2.vhdl
+
+echo "Test successful"