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author | Tristan Gingold <tgingold@free.fr> | 2022-12-16 07:31:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-12-16 07:31:16 +0100 |
commit | 27c2badb6d3d0f3e84b5bfe53770bd911679db42 (patch) | |
tree | a6aa728ad85ef757a20dbfc2003dc753b25b0c6f /testsuite | |
parent | 52168ebce2bee72c122e5e4661c201664b5f3b8b (diff) | |
download | ghdl-27c2badb6d3d0f3e84b5bfe53770bd911679db42.tar.gz ghdl-27c2badb6d3d0f3e84b5bfe53770bd911679db42.tar.bz2 ghdl-27c2badb6d3d0f3e84b5bfe53770bd911679db42.zip |
testsuite/gna: add a test for #2271
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue2271/ent.vhdl | 21 | ||||
-rwxr-xr-x | testsuite/gna/issue2271/testsuite.sh | 10 |
2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/issue2271/ent.vhdl b/testsuite/gna/issue2271/ent.vhdl new file mode 100644 index 000000000..1d5ea6ff1 --- /dev/null +++ b/testsuite/gna/issue2271/ent.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity; + +architecture behaviour of ent is + component comp is + port ( + d : in std_logic; + q : out std_logic + ); + end component; +begin + + comp : comp + port map ( + d => '0', + q => open + ); +end architecture; diff --git a/testsuite/gna/issue2271/testsuite.sh b/testsuite/gna/issue2271/testsuite.sh new file mode 100755 index 000000000..a679ec9c9 --- /dev/null +++ b/testsuite/gna/issue2271/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +if $GHDL -c ent.vhdl -e ent; then + echo "Error expected" + exit 1 +fi + +echo "Test successful" |