testsuite/gna: add a test for #1814

3 files changed, 72 insertions, 0 deletions

diff --git a/testsuite/gna/issue1814/ent.vhdl b/testsuite/gna/issue1814/ent.vhdl
new file mode 100644
index 000000000..5d63ff455
--- /dev/null
+++ b/testsuite/gna/issue1814/ent.vhdl
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ent is
+generic (
+  W : integer := 1
+);
+port (
+  wen : in std_logic_vector(W-1 downto 0)
+);
+end entity ent;
+
+architecture rtl of ent is
+begin
+
+  process begin
+    report "Hello world from ent." severity note;
+    wait;
+  end process;
+
+end rtl;
diff --git a/testsuite/gna/issue1814/testsuite.sh b/testsuite/gna/issue1814/testsuite.sh
new file mode 100755
index 000000000..859ea8529
--- /dev/null
+++ b/testsuite/gna/issue1814/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze ent.vhdl top.vhdl
+elab_simulate top
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue1814/top.vhdl b/testsuite/gna/issue1814/top.vhdl
new file mode 100644
index 000000000..819db57c0
--- /dev/null
+++ b/testsuite/gna/issue1814/top.vhdl
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity top is
+generic (
+  W : integer := 1
+);
+end entity top;
+
+architecture rtl of top is
+
+  signal write : std_logic;
+  -- workaround
+  signal wen   : std_logic_vector(W-1 downto 0);
+
+begin
+
+  process begin
+    report "Hello world from top" severity note;
+    wait;
+  end process;
+
+  write <= '0';
+
+  -- workaround
+  wen <= (others => write);
+
+  u_ent: entity work.ent
+  generic map(
+    W => W
+  )
+  port map(
+  -- workaround
+    wen => (others => write)
+--  wen => wen
+  );
+
+end rtl;