pyGHDL.dom: improvements (#1848)

# New Features
 
* Translate null statements.
* Sequential procedure call.
 * Concurrent assert statement (but without condition)
    This needs either PSL translations or help from @tgingold to have partial elaboration to a PSL assert becomes a normal VHDL assertion like in VHDL-93.
* Translate sensitivity lists.
 
# Changes
 
* None
 
# Bug fixes
 
* Changes due to typo in pyVHDLModel for `Choises`.

1 files changed, 10 insertions, 0 deletions

diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index b4906e211..96e9433d9 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -94,6 +94,7 @@ begin
 				Q <= D after 10 ns;
 			else
 				Q <= std_logic_vector(unsigned(Q) + 1);
+				counter.increment(1);
 			end if;
 		end if;
 
@@ -133,6 +134,10 @@ begin
 
 	a <= b;
 
+	assert false;
+	assert false report "some error";
+	assert false severity warning;
+	assert false report "some note" severity note;
 
 	inst1: entity work.counter1(rtl)
 		generic map (
@@ -210,6 +215,11 @@ begin
 				constant G7 : boolean := False;
 			begin
 				inst: component Case5689Dummy;
+				process
+				begin
+					null;
+					wait;
+				end process;
 
 		when others =>
 				constant G8 : boolean := False;