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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-23 13:29:23 +0200 |
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committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-23 13:29:23 +0200 |
commit | 11f1ebbc80250555474cfe22e1db10553e112a11 (patch) | |
tree | d50bd491e0f077a951ce81332546a6eb29e2e156 /testsuite | |
parent | d97e2079a633736d0323e915cabff5f91cfd4ebe (diff) | |
download | ghdl-11f1ebbc80250555474cfe22e1db10553e112a11.tar.gz ghdl-11f1ebbc80250555474cfe22e1db10553e112a11.tar.bz2 ghdl-11f1ebbc80250555474cfe22e1db10553e112a11.zip |
Handle 'Subtype_Definition' in record definitions.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/pyunit/Current.vhdl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 874844590..ff03e1d04 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -21,6 +21,7 @@ end entity entity_1; architecture behav of entity_1 is constant MAX : positive := -25; signal rst : std_logic := foo('U'); +-- signal vec : bit_vector(pack.input'bar'range); type newInt is range -4 to 3; type newFp is range 4.3 downto -3.9; @@ -28,6 +29,8 @@ architecture behav of entity_1 is type rec is record elem1 : bit; elem2 : boolean; + elem3 : integer_vector(3 downto 0); + elem4 : natural range 7 to 8; end record; type enum is (e1, e2, e3); type acc is access bar; |