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authorTristan Gingold <tgingold@free.fr>2020-01-10 19:34:12 +0100
committerTristan Gingold <tgingold@free.fr>2020-01-10 19:34:12 +0100
commit11a5be93a2b037dae7ba6785ea10cb17c7fef2b7 (patch)
tree58bd904c445c836b0f77000ced678cd0cec453a8 /testsuite
parent52f75c4ee97525a3dbd432cde1bfd792922ba5ad (diff)
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testsuite/synth: add a test for #1074
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue1074/blinky.vhdl37
-rwxr-xr-xtestsuite/synth/issue1074/testsuite.sh7
2 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/synth/issue1074/blinky.vhdl b/testsuite/synth/issue1074/blinky.vhdl
new file mode 100644
index 000000000..5f5acbb0d
--- /dev/null
+++ b/testsuite/synth/issue1074/blinky.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+entity blinky is
+port (
+ clk : in std_logic;
+ led : out std_logic
+ );
+end blinky;
+
+architecture rtl of blinky is
+constant max_count : natural := 48000000;
+signal rst : std_logic;
+begin
+ rst <= '0';
+ -- 0 to max_count counter
+ counter : process(clk, Rst)
+ variable count : natural range 0 to max_count;
+ begin
+ if rising_edge(clk) then
+ if count < max_count/2 then
+ count := count + 1;
+ led <= '1';
+ elsif count < max_count then
+ led <= '0';
+ count := count + 1;
+ else
+ led <= '1';
+ count := 0;
+ end if;
+ elsif rst = '1' then
+ count := 0;
+ led <= '1';
+ end if;
+ end process counter;
+end rtl;
diff --git a/testsuite/synth/issue1074/testsuite.sh b/testsuite/synth/issue1074/testsuite.sh
new file mode 100755
index 000000000..0b2048804
--- /dev/null
+++ b/testsuite/synth/issue1074/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+! synth blinky.vhdl -e
+
+echo "Test successful"