testsuite/synth: add test for #1100.

4 files changed, 118 insertions, 0 deletions

diff --git a/testsuite/synth/issue1100/repro.vhdl b/testsuite/synth/issue1100/repro.vhdl
new file mode 100644
index 000000000..9215a19a0
--- /dev/null
+++ b/testsuite/synth/issue1100/repro.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro is
+  port (val : std_logic_vector (63 downto 0);
+        iperm : std_logic_vector (3*8 - 1 downto 0);
+        en : std_ulogic;
+        res : out std_logic_vector (63 downto 0));
+end entity repro;
+
+architecture behaviour of repro is
+    type arecordtype is record
+        valid : std_ulogic;
+        write_data : std_ulogic_vector(63 downto 0);
+    end record;
+
+    signal a : arecordtype;
+
+    subtype byte_index_t is unsigned(2 downto 0);
+    type permutation_t is array(0 to 7) of byte_index_t;
+    signal perm : permutation_t := (others => "000");
+begin
+    writeback_1: process(all)
+        variable j : integer;
+    begin
+        for i in 0 to 7 loop
+          j := to_integer(perm(i)) * 8;
+          res(i * 8 + 7 downto i * 8) <= a.write_data(j + 7 downto j);
+        end loop;
+    end process;
+
+    a.valid <= en;
+    a.write_data <= val;
+
+    process (iperm) is
+    begin
+      for i in 0 to 7 loop
+        perm (i) <= unsigned (iperm (i*3 + 2 downto i*3));
+      end loop;
+    end process;
+end;
diff --git a/testsuite/synth/issue1100/tb_repro.vhdl b/testsuite/synth/issue1100/tb_repro.vhdl
new file mode 100644
index 000000000..f1394d1ad
--- /dev/null
+++ b/testsuite/synth/issue1100/tb_repro.vhdl
@@ -0,0 +1,30 @@
+entity tb_repro is
+end tb_repro;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro is
+  signal val   : std_logic_vector (63 downto 0);
+  signal iperm : std_logic_vector (3*8 - 1 downto 0) := (others => '0');
+  signal en    : std_ulogic;
+  signal res   : std_logic_vector (63 downto 0);
+begin
+  dut: entity work.repro
+    port map (val, iperm, en, res);
+
+  process
+  begin
+    val <= x"01_23_45_67_89_ab_cd_ef";
+    en <= '1';
+    iperm <= o"76543210";
+    wait for 1 ns;
+    assert res = x"01_23_45_67_89_ab_cd_ef"severity failure;
+
+    iperm <= o"01234567";
+    wait for 1 ns;
+    assert res = x"ef_cd_ab_89_67_45_23_01"
+      report to_hstring(res) severity failure;
+wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1100/test.vhdl b/testsuite/synth/issue1100/test.vhdl
new file mode 100644
index 000000000..313b7d238
--- /dev/null
+++ b/testsuite/synth/issue1100/test.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+
+architecture behaviour of test is
+    type arecordtype is record
+        valid : std_ulogic;
+        write_data : std_ulogic_vector(63 downto 0);
+    end record;
+
+    signal a : arecordtype;
+
+    subtype byte_index_t is unsigned(2 downto 0);
+    type permutation_t is array(0 to 7) of byte_index_t;
+    signal perm : permutation_t;
+    signal data_permuted : std_ulogic_vector(63 downto 0);
+begin
+    writeback_1: process(all)
+        variable j : integer;
+    begin
+        for i in 0 to 7 loop
+            j := to_integer(perm(i)) * 8;
+            data_permuted(i * 8 + 7 downto i * 8) <= a.write_data(j + 7 downto j);
+        end loop;
+    end process;
+end;
diff --git a/testsuite/synth/issue1100/testsuite.sh b/testsuite/synth/issue1100/testsuite.sh
new file mode 100755
index 000000000..861e2e180
--- /dev/null
+++ b/testsuite/synth/issue1100/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in repro; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"