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author | Tristan Gingold <tgingold@free.fr> | 2023-04-13 07:58:58 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-13 08:02:19 +0200 |
commit | 0a123ce9b96270447fac2c406b252ad8ffaf9ade (patch) | |
tree | b9b41b18389613897d69fd125f7946743812591b /testsuite | |
parent | 42a95f5ce54847a01cb0cb47520678c42a04165d (diff) | |
download | ghdl-0a123ce9b96270447fac2c406b252ad8ffaf9ade.tar.gz ghdl-0a123ce9b96270447fac2c406b252ad8ffaf9ade.tar.bz2 ghdl-0a123ce9b96270447fac2c406b252ad8ffaf9ade.zip |
testsuite/gna: add a reproducer for #2395
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue2395/test.vhdl | 64 | ||||
-rwxr-xr-x | testsuite/gna/issue2395/testsuite.sh | 11 |
2 files changed, 75 insertions, 0 deletions
diff --git a/testsuite/gna/issue2395/test.vhdl b/testsuite/gna/issue2395/test.vhdl new file mode 100644 index 000000000..7b467938e --- /dev/null +++ b/testsuite/gna/issue2395/test.vhdl @@ -0,0 +1,64 @@ +library ieee ; + use ieee.std_logic_1164.all ; + +package axi4s is + + type axis_t is record + data : std_ulogic_vector ; + dest : std_ulogic_vector ; + id : std_ulogic_vector ; + strb : std_ulogic_vector ; + keep : std_ulogic_vector ; + user : std_ulogic_vector ; + last : std_ulogic ; + valid : std_ulogic ; + ready : std_ulogic ; + end record ; + + type axis_array_t is array(natural range <>) of axis_t ; + + package make is + generic ( + DATA_BYTES : positive := 4 ; + DEST_WIDTH : natural := 0 ; + ID_WIDTH : natural := 0 ; + USER_WIDTH : natural := 0 + ) ; + + subtype DATA_RANGE is natural range DATA_BYTES*8-1 downto 0 ; + subtype DEST_RANGE is natural range DEST_WIDTH-1 downto 0 ; + subtype ID_RANGE is natural range ID_WIDTH-1 downto 0 ; + subtype KEEP_RANGE is natural range DATA_BYTES-1 downto 0 ; + subtype USER_RANGE is natural range USER_WIDTH-1 downto 0 ; + + subtype axis_t is axi4s.axis_t( + data(DATA_RANGE), + dest(DEST_RANGE), + id(ID_RANGE), + keep(KEEP_RANGE), + strb(KEEP_RANGE), + user(USER_RANGE) + ) ; + + end package ; + +end package ; + +package axis32 is new work.axi4s.make ; + +entity test is + port ( + clock : in bit ; + reset : in bit ; + rx : inout work.axis32.axis_t ; + tx : inout work.axi4s.axis_t(data(31 downto 0), dest(-1 downto 0), id(-1 downto 0), keep(3 downto 0), strb(-1 downto 0), user(-1 downto 0)) + ) ; +end entity ; + +architecture arch of test is + +begin + + -- do nothing for now + +end architecture ; diff --git a/testsuite/gna/issue2395/testsuite.sh b/testsuite/gna/issue2395/testsuite.sh new file mode 100755 index 000000000..1d84c0f57 --- /dev/null +++ b/testsuite/gna/issue2395/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" |