Import vests testsuite

4 files changed, 47 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
new file mode 100644
index 000000000..d3809c57d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
@@ -0,0 +1,16 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : bit_vector( 3 downto 0 );
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= "1001";
+    wait for 1 fs;
+    assert sig = "1001" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+    
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl
new file mode 100644
index 000000000..c233fdf4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl
@@ -0,0 +1,16 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= 1;
+    wait for 1 fs;
+    assert sig = 1 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+    
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl
new file mode 100644
index 000000000..91e45ebc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl
@@ -0,0 +1,13 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert sig = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore
new file mode 100644
index 000000000..19eb705c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore
@@ -0,0 +1,2 @@
+work._savant_lib
+work.sym