testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#179

4 files changed, 120 insertions, 0 deletions

diff --git a/testsuite/synth/synth179/repro1.vhdl b/testsuite/synth/synth179/repro1.vhdl
new file mode 100644
index 000000000..f6fd480fa
--- /dev/null
+++ b/testsuite/synth/synth179/repro1.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (aclr : std_logic;
+        clk : std_logic;
+        din : std_logic;
+        dout : out std_logic);
+end;
+
+architecture behav of repro1 is
+  signal r : std_logic;
+begin
+  process (aclr, clk) is
+  begin
+    if rising_edge (clk) then
+      r <= din;
+    end if;
+    if aclr = '1' then
+      r <= '0';
+    end if;
+  end process;
+
+  dout <= r;
+end behav;
diff --git a/testsuite/synth/synth179/repro2.vhdl b/testsuite/synth/synth179/repro2.vhdl
new file mode 100644
index 000000000..099578aaf
--- /dev/null
+++ b/testsuite/synth/synth179/repro2.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+  port (aclr : std_logic;
+        clk : std_logic;
+        din : std_logic;
+        dout : out std_logic);
+end;
+
+architecture behav of repro2 is
+  signal r : std_logic;
+begin
+  process (aclr, clk) is
+    variable init : boolean := false;
+  begin
+    if not init then
+      r <= '0';
+      init := true;
+    end if;
+
+    if rising_edge (clk) then
+      r <= din;
+    end if;
+    if aclr = '1' then
+      r <= '0';
+    end if;
+  end process;
+
+  dout <= r;
+end behav;
diff --git a/testsuite/synth/synth179/test.vhdl b/testsuite/synth/synth179/test.vhdl
new file mode 100644
index 000000000..0d8b1715c
--- /dev/null
+++ b/testsuite/synth/synth179/test.vhdl
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+-- use ieee.math_real.all;
+
+LIBRARY altera_mf;
+-- USE altera_mf.altera_mf_components.all;
+
+entity test is
+  port (
+    clk     : in std_logic;
+    rst     : in std_logic;
+    re     : in std_logic;
+    we     : in std_logic;
+    src_in  : in std_logic_vector(255 downto 0);
+    src_out : out std_logic_vector(255 downto 0)
+  );
+end entity;
+
+architecture rtl of test is
+
+begin
+
+  scfifo_rx : entity altera_mf.scfifo
+  generic map (
+    lpm_width => 256,
+    lpm_widthu => 2,
+    lpm_numwords => 2,
+    lpm_showahead => "OFF",
+    lpm_hint => "USE_EAB=ON",
+    ram_block_type => "AUTO",
+    intended_device_family => "Arria 10",
+    almost_full_value => 0,
+    almost_empty_value => 0,
+    overflow_checking => "ON",
+    underflow_checking => "ON",
+    allow_rwcycle_when_full => "OFF",
+    add_ram_output_register => "OFF",
+    use_eab => "ON",
+    lpm_type => "scfifo",
+    enable_ecc => "false",
+    maximum_depth => 0
+  )
+  port map (
+    aclr => rst,
+    clock => clk,
+    wrreq => we,
+    data => src_in,
+    full => open,
+    rdreq => re,
+    q => src_out,
+    empty => open,
+    usedw => open
+  );
+
+end architecture;
diff --git a/testsuite/synth/synth179/testsuite.sh b/testsuite/synth/synth179/testsuite.sh
new file mode 100755
index 000000000..d84ce05fe
--- /dev/null
+++ b/testsuite/synth/synth179/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro1
+synth_failure repro2.vhdl -e
+
+echo "Test successful"