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author | Tristan Gingold <tgingold@free.fr> | 2021-12-06 20:47:31 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-12-06 20:47:54 +0100 |
commit | f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7 (patch) | |
tree | eb70942c2bcf2f7d73c865724f4554cdf4e42ae4 /testsuite/synth | |
parent | 88425cb365578cacd46939d93f837b2ac7b0d5e8 (diff) | |
download | ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.tar.gz ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.tar.bz2 ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.zip |
testsuite/synth: add a test for #938
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue938/ent.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/issue938/latches.vhdl | 21 | ||||
-rw-r--r-- | testsuite/synth/issue938/tb_latches.vhdl | 52 | ||||
-rwxr-xr-x | testsuite/synth/issue938/testsuite.sh | 16 |
4 files changed, 109 insertions, 0 deletions
diff --git a/testsuite/synth/issue938/ent.vhdl b/testsuite/synth/issue938/ent.vhdl new file mode 100644 index 000000000..6d38a9548 --- /dev/null +++ b/testsuite/synth/issue938/ent.vhdl @@ -0,0 +1,20 @@ +entity ent is + port ( + r : in bit; + s : in bit; + q : out bit + ); +end entity; + +architecture a of ent is +begin + process(r, s) + begin + if r = '1' then + q <= '0'; + elsif s = '1' then + q <= '1'; + end if; + end process; +end; + diff --git a/testsuite/synth/issue938/latches.vhdl b/testsuite/synth/issue938/latches.vhdl new file mode 100644 index 000000000..0fcd7a8ba --- /dev/null +++ b/testsuite/synth/issue938/latches.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity latches is + port( + G, D, CLR : in std_logic; + Q : out std_logic + ); +end latches; + +architecture archi of latches is +begin + process(CLR, D, G) + begin + if (CLR = '1') then + Q <= '0'; + elsif (G = '1') then + Q <= D; + end if; + end process; +end archi; diff --git a/testsuite/synth/issue938/tb_latches.vhdl b/testsuite/synth/issue938/tb_latches.vhdl new file mode 100644 index 000000000..75e6e8c2f --- /dev/null +++ b/testsuite/synth/issue938/tb_latches.vhdl @@ -0,0 +1,52 @@ +entity tb_latches is +end tb_latches; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_latches is + signal g : std_logic; + signal d : std_logic; + signal clr : std_logic; + signal q : std_logic; +begin + dut: entity work.latches + port map (g, d, clr, q); + + process + begin + clr <= '1'; + g <= '0'; + wait for 1 ns; + assert q = '0' severity failure; + + clr <= '0'; + wait for 1 ns; + assert q = '0' severity failure; + + g <= '1'; + d <= '1'; + wait for 1 ns; + assert q = '1' severity failure; + + g <= '0'; + d <= '0'; + wait for 1 ns; + assert q = '1' severity failure; + + g <= '1'; + d <= '0'; + wait for 1 ns; + assert q = '0' severity failure; + + g <= '1'; + d <= '1'; + wait for 1 ns; + assert q = '1' severity failure; + + clr <= '1'; + wait for 1 ns; + assert q = '0' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue938/testsuite.sh b/testsuite/synth/issue938/testsuite.sh new file mode 100755 index 000000000..ea5722dfc --- /dev/null +++ b/testsuite/synth/issue938/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze latches.vhdl tb_latches.vhdl +elab_simulate tb_latches + +clean + +synth --latches latches.vhdl -e > syn_latches.vhdl +analyze syn_latches.vhdl tb_latches.vhdl +elab_simulate tb_latches + +clean + +echo "Test successful" |