testsuite/synth: testcase for conditional signal assignment.

3 files changed, 61 insertions, 0 deletions

diff --git a/testsuite/synth/issue40/tb_testcase.vhdl b/testsuite/synth/issue40/tb_testcase.vhdl
new file mode 100644
index 000000000..3ed89e61c
--- /dev/null
+++ b/testsuite/synth/issue40/tb_testcase.vhdl
@@ -0,0 +1,26 @@
+entity tb_testcase is
+end tb_testcase;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_testcase is
+  signal di : std_logic;
+  signal do : std_logic;
+begin
+  dut: entity work.testcase
+    port map (data_in => di, data_out => do);
+
+  process
+  begin
+    di <= '1';
+    wait for 1 ns;
+    assert do = '0' severity failure;
+    
+    di <= '0';
+    wait for 1 ns;
+    assert do = '1' severity failure;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue40/testcase.vhdl b/testsuite/synth/issue40/testcase.vhdl
new file mode 100644
index 000000000..8055fac85
--- /dev/null
+++ b/testsuite/synth/issue40/testcase.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+        port(
+                data_in  : in std_ulogic;
+                data_out : out std_ulogic
+        );
+end entity testcase;
+
+architecture behaviour of testcase is
+begin
+        comb : process(all)
+        begin
+                data_out <= '1' when data_in = '0' else '0';
+        end process;
+end architecture behaviour;
diff --git a/testsuite/synth/issue40/testsuite.sh b/testsuite/synth/issue40/testsuite.sh
new file mode 100755
index 000000000..54d4ea0ed
--- /dev/null
+++ b/testsuite/synth/issue40/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in testcase; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"