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author | Tristan Gingold <tgingold@free.fr> | 2019-07-10 18:57:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-10 19:06:07 +0200 |
commit | bd6da20d2370c512c4ef46349391bfc8c83ded68 (patch) | |
tree | e973fd127fa8121b3b675ac235a2ccfc122d0723 /testsuite/synth | |
parent | 0ef59aec0acc050d09dc74c047aa224081c4eced (diff) | |
download | ghdl-bd6da20d2370c512c4ef46349391bfc8c83ded68.tar.gz ghdl-bd6da20d2370c512c4ef46349391bfc8c83ded68.tar.bz2 ghdl-bd6da20d2370c512c4ef46349391bfc8c83ded68.zip |
synth: add a simple test for instantiation.
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/comp01/and3.vhdl | 12 | ||||
-rw-r--r-- | testsuite/synth/comp01/and6.vhdl | 17 | ||||
-rw-r--r-- | testsuite/synth/comp01/and6comp.vhdl | 21 | ||||
-rw-r--r-- | testsuite/synth/comp01/tb_and6.vhdl | 37 | ||||
-rwxr-xr-x | testsuite/synth/comp01/testsuite.sh | 18 |
5 files changed, 105 insertions, 0 deletions
diff --git a/testsuite/synth/comp01/and3.vhdl b/testsuite/synth/comp01/and3.vhdl new file mode 100644 index 000000000..be0a0c821 --- /dev/null +++ b/testsuite/synth/comp01/and3.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity and3 is + port (a, b, c : std_logic; + o : out std_logic); +end and3; + +architecture behav of and3 is +begin + o <= a and b and c; +end behav; diff --git a/testsuite/synth/comp01/and6.vhdl b/testsuite/synth/comp01/and6.vhdl new file mode 100644 index 000000000..2aadd5261 --- /dev/null +++ b/testsuite/synth/comp01/and6.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity and6 is + port (i0, i1, i2, i3, i4, i5 : std_logic; + o : out std_logic); +end and6; + +architecture behav of and6 is + signal t1, t2 : std_logic; +begin + a1: entity work.and3 + port map (i0, i1, i2, t1); + a2: entity work.and3 + port map (i3, i4, i5, t2); + o <= t1 and t2; +end behav; diff --git a/testsuite/synth/comp01/and6comp.vhdl b/testsuite/synth/comp01/and6comp.vhdl new file mode 100644 index 000000000..8cdb8f821 --- /dev/null +++ b/testsuite/synth/comp01/and6comp.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity and6comp is + port (i0, i1, i2, i3, i4, i5 : std_logic; + o : out std_logic); +end and6comp; + +architecture behav of and6comp is + component and3 is + port (a, b, c : std_logic; + o : out std_logic); + end component; + signal t1, t2 : std_logic; +begin + a1: and3 + port map (i0, i1, i2, t1); + a2: and3 + port map (i3, i4, i5, t2); + o <= t1 and t2; +end behav; diff --git a/testsuite/synth/comp01/tb_and6.vhdl b/testsuite/synth/comp01/tb_and6.vhdl new file mode 100644 index 000000000..177592373 --- /dev/null +++ b/testsuite/synth/comp01/tb_and6.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_and6 is +end tb_and6; + +architecture behav of tb_and6 is + signal i0, i1, i2, i3, i4, i5 : std_logic; + signal o : std_logic; + +begin + dut : entity work.and6 + port map (i0 => i0, i1 => i1, i2 => i2, i3 => i4, i4 => i4, + i5 => i5, o => o); + + process + constant v0 : std_logic_vector := b"1011"; + constant v1 : std_logic_vector := b"1111"; + constant v2 : std_logic_vector := b"1111"; + constant v3 : std_logic_vector := b"1111"; + constant v4 : std_logic_vector := b"1111"; + constant v5 : std_logic_vector := b"1101"; + constant ov : std_logic_vector := b"1001"; + begin + for i in ov'range loop + i0 <= v0 (i); + i1 <= v1 (i); + i2 <= v2 (i); + i3 <= v3 (i); + i4 <= v4 (i); + i5 <= v5 (i); + wait for 1 ns; + assert o = ov(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/comp01/testsuite.sh b/testsuite/synth/comp01/testsuite.sh new file mode 100755 index 000000000..c16175e4c --- /dev/null +++ b/testsuite/synth/comp01/testsuite.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +. ../../testenv.sh + +#! /bin/sh + +. ../../testenv.sh + +analyze and3.vhdl and6.vhdl tb_and6.vhdl +elab_simulate tb_and6 +clean + +synth and3.vhdl and6.vhdl -e and6 > syn_and6.vhdl +analyze syn_and6.vhdl tb_and6.vhdl +elab_simulate tb_and6 +clean + +echo "Test successful" |