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author | Tristan Gingold <tgingold@free.fr> | 2021-03-13 07:48:20 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-03-13 08:01:46 +0100 |
commit | 8d8b9d5449385b5609ec0d867ce32c545a814bb6 (patch) | |
tree | 450c21e708141f41843ce0a31662ef4c907cf9a6 /testsuite/synth | |
parent | 301c417faec48049ab3ffe208bdbbc6098f482ad (diff) | |
download | ghdl-8d8b9d5449385b5609ec0d867ce32c545a814bb6.tar.gz ghdl-8d8b9d5449385b5609ec0d867ce32c545a814bb6.tar.bz2 ghdl-8d8b9d5449385b5609ec0d867ce32c545a814bb6.zip |
testsuite/synth: add a test for #1680
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1680/test_fail.vhdl | 33 | ||||
-rwxr-xr-x | testsuite/synth/issue1680/testsuite.sh | 7 |
2 files changed, 40 insertions, 0 deletions
diff --git a/testsuite/synth/issue1680/test_fail.vhdl b/testsuite/synth/issue1680/test_fail.vhdl new file mode 100644 index 000000000..660558bce --- /dev/null +++ b/testsuite/synth/issue1680/test_fail.vhdl @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_fail is + port( + reset_n_i : in std_ulogic; + clock_i : in std_ulogic; + value_o : out std_ulogic + ); +end test_fail; + +architecture beh of test_fail is + + signal value_s: std_ulogic; + + attribute nomerge : string; + attribute nomerge of value_s : signal is ""; + +begin + + regs: process (clock_i, reset_n_i) + begin + if reset_n_i = '0' then + value_s <= '0'; + elsif rising_edge(clock_i) then + value_s <= not value_s; + end if; + end process; + + value_o <= value_s; + +end architecture; + diff --git a/testsuite/synth/issue1680/testsuite.sh b/testsuite/synth/issue1680/testsuite.sh new file mode 100755 index 000000000..9d823928f --- /dev/null +++ b/testsuite/synth/issue1680/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only test_fail + +echo "Test successful" |