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author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:32:59 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:32:59 +0200 |
commit | 5b00e825e9befedcfe0806d380218286ddce42ce (patch) | |
tree | 24831f431cfcaa2b9ef93df027555a9ecea3d9c5 /testsuite/synth | |
parent | d469d3bfe180707927a04a8d1e69a1276c88bb7c (diff) | |
download | ghdl-5b00e825e9befedcfe0806d380218286ddce42ce.tar.gz ghdl-5b00e825e9befedcfe0806d380218286ddce42ce.tar.bz2 ghdl-5b00e825e9befedcfe0806d380218286ddce42ce.zip |
testsuite/synth: add testcase for #952
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/oper01/cmp02.vhdl | 24 | ||||
-rw-r--r-- | testsuite/synth/oper01/tb_cmp02.vhdl | 62 | ||||
-rwxr-xr-x | testsuite/synth/oper01/testsuite.sh | 2 |
3 files changed, 87 insertions, 1 deletions
diff --git a/testsuite/synth/oper01/cmp02.vhdl b/testsuite/synth/oper01/cmp02.vhdl new file mode 100644 index 000000000..71c6c72a7 --- /dev/null +++ b/testsuite/synth/oper01/cmp02.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity cmp02 is + port (l : std_logic_vector(3 downto 0); + r : natural; + eq : out std_logic; + ne : out std_logic; + lt : out std_logic; + le : out std_logic; + ge : out std_logic; + gt : out std_logic); +end cmp02; + +architecture behav of cmp02 is +begin + eq <= '1' when unsigned(l) = r else '0'; + ne <= '1' when unsigned(l) /= r else '0'; + lt <= '1' when unsigned(l) < r else '0'; + le <= '1' when unsigned(l) <= r else '0'; + gt <= '1' when unsigned(l) > r else '0'; + ge <= '1' when unsigned(l) >= r else '0'; +end behav; diff --git a/testsuite/synth/oper01/tb_cmp02.vhdl b/testsuite/synth/oper01/tb_cmp02.vhdl new file mode 100644 index 000000000..9165d14a0 --- /dev/null +++ b/testsuite/synth/oper01/tb_cmp02.vhdl @@ -0,0 +1,62 @@ +entity tb_cmp02 is +end tb_cmp02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_cmp02 is + signal l : std_logic_vector(3 downto 0); + signal r : natural; + signal eq : std_logic; + signal ne : std_logic; + signal lt : std_logic; + signal le : std_logic; + signal ge : std_logic; + signal gt : std_logic; +begin + cmp02_1: entity work.cmp02 + port map ( + l => l, + r => r, + eq => eq, + ne => ne, + lt => lt, + le => le, + ge => ge, + gt => gt); + + process + begin + l <= x"5"; + r <= 7; + wait for 1 ns; + assert eq = '0' severity failure; + assert ne = '1' severity failure; + assert lt = '1' severity failure; + assert le = '1' severity failure; + assert ge = '0' severity failure; + assert gt = '0' severity failure; + + l <= x"a"; + r <= 7; + wait for 1 ns; + assert eq = '0' severity failure; + assert ne = '1' severity failure; + assert lt = '0' severity failure; + assert le = '0' severity failure; + assert ge = '1' severity failure; + assert gt = '1' severity failure; + + l <= x"9"; + r <= 9; + wait for 1 ns; + assert eq = '1' severity failure; + assert ne = '0' severity failure; + assert lt = '0' severity failure; + assert le = '1' severity failure; + assert ge = '1' severity failure; + assert gt = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/oper01/testsuite.sh b/testsuite/synth/oper01/testsuite.sh index 6ffd137c4..3f524a47e 100755 --- a/testsuite/synth/oper01/testsuite.sh +++ b/testsuite/synth/oper01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in cmp01 match01; do +for t in cmp01 cmp02 match01; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t --ieee-asserts=disable-at-0 clean |