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author | Tristan Gingold <tgingold@free.fr> | 2020-01-16 18:27:21 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-16 18:27:21 +0100 |
commit | 3f1b94705e7275aebb9ab64b36b69c32cc3372ed (patch) | |
tree | 6dfd945ceca067b5e526fabe39417c73cac062f6 /testsuite/synth | |
parent | 16ec60e45d913be37e2bb90473c053bf2cc87a74 (diff) | |
download | ghdl-3f1b94705e7275aebb9ab64b36b69c32cc3372ed.tar.gz ghdl-3f1b94705e7275aebb9ab64b36b69c32cc3372ed.tar.bz2 ghdl-3f1b94705e7275aebb9ab64b36b69c32cc3372ed.zip |
testcase/synth: add reproducer from #1090
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1090/bootrom.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/issue1090/simple_ram-orig.vhdl | 51 | ||||
-rw-r--r-- | testsuite/synth/issue1090/simple_ram.vhdl | 73 | ||||
-rw-r--r-- | testsuite/synth/issue1090/tb_simple_ram.vhdl | 46 | ||||
-rwxr-xr-x | testsuite/synth/issue1090/testsuite.sh | 16 |
5 files changed, 206 insertions, 0 deletions
diff --git a/testsuite/synth/issue1090/bootrom.vhdl b/testsuite/synth/issue1090/bootrom.vhdl new file mode 100644 index 000000000..458e60274 --- /dev/null +++ b/testsuite/synth/issue1090/bootrom.vhdl @@ -0,0 +1,20 @@ +-- Machine generated from ram.img. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package bootrom is + type rom_t is array (0 to 127) of std_logic_vector(31 downto 0); + constant rom : rom_t := ( + x"00000110", + x"00001ffc", + x"00000110", +-- more stuff, doesn't matter as long as it fits... + x"23811fac", + x"00afffac", + others => x"00000000" ); + +end package; + +package body bootrom is +end package body; diff --git a/testsuite/synth/issue1090/simple_ram-orig.vhdl b/testsuite/synth/issue1090/simple_ram-orig.vhdl new file mode 100644 index 000000000..6cb4aa6f1 --- /dev/null +++ b/testsuite/synth/issue1090/simple_ram-orig.vhdl @@ -0,0 +1,51 @@ +-- A simple pre-initalized RAM, which reads from a binary file at synthesis time +-- single 32 bit read/write port. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.bootrom.all; + +entity simple_ram is + generic ( + -- 32-bit read/write port. ADDR_WIDTH is in bytes, not words. + ADDR_WIDTH : integer := 8 -- default 32k + ); + port ( + clk : in std_logic; + + en : in std_logic; + raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0); + do : out std_logic_vector(31 downto 0); + + we : in std_logic_vector(3 downto 0); + waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0); + di : in std_logic_vector(31 downto 0) + ); +end simple_ram; + +architecture behavioral of simple_ram is + constant NUM_WORDS : integer := 2**(ADDR_WIDTH - 2); + signal ram : rom_t := work.bootrom.rom; -- FIXME init internal error +begin + + process (clk, en) + variable read : std_logic_vector(31 downto 0); + begin + if clk'event and clk = '1' then -- and en = '1' then -- Unsupported: clock enable + if we(3) = '1' then + ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24); + end if; + if we(2) = '1' then + ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16); + end if; + if we(1) = '1' then + ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 ); + end if; + if we(0) = '1' then + ram(to_integer(unsigned(waddr)))(7 downto 0 ) <= di(7 downto 0 ); + end if; + read := ram(to_integer(unsigned(raddr))); + do <= read; + end if; + end process; +end behavioral; diff --git a/testsuite/synth/issue1090/simple_ram.vhdl b/testsuite/synth/issue1090/simple_ram.vhdl new file mode 100644 index 000000000..345083850 --- /dev/null +++ b/testsuite/synth/issue1090/simple_ram.vhdl @@ -0,0 +1,73 @@ +-- Machine generated from ram.img. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package bootrom is + type rom_t is array (0 to 127) of std_logic_vector(31 downto 0); + constant rom : rom_t := ( + x"00000110", + x"00001ffc", + x"00000110", +-- more stuff, doesn't matter as long as it fits... + x"23811fac", + x"00afffac", + others => x"00000000" ); + +end package; + +package body bootrom is +end package body; + +-- A simple pre-initalized RAM, which reads from a binary file at synthesis time +-- single 32 bit read/write port. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity simple_ram is + generic ( + -- 32-bit read/write port. ADDR_WIDTH is in bytes, not words. + ADDR_WIDTH : integer := 8 -- default 32k + ); + port ( + clk : in std_logic; + + en : in std_logic; + raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0); + do : out std_logic_vector(31 downto 0); + + we : in std_logic_vector(3 downto 0); + waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0); + di : in std_logic_vector(31 downto 0) + ); +end simple_ram; + +use work.bootrom.all; + +architecture behavioral of simple_ram is + constant NUM_WORDS : integer := 2**(ADDR_WIDTH - 2); + signal ram : rom_t := work.bootrom.rom; -- FIXME init internal error +begin + + process (clk, en) + variable read : std_logic_vector(31 downto 0); + begin + if clk'event and clk = '1' and en = '1' then -- Unsupported: clock enable + if we(3) = '1' then + ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24); + end if; + if we(2) = '1' then + ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16); + end if; + if we(1) = '1' then + ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 ); + end if; + if we(0) = '1' then + ram(to_integer(unsigned(waddr)))(7 downto 0 ) <= di(7 downto 0 ); + end if; + read := ram(to_integer(unsigned(raddr))); + do <= read; + end if; + end process; +end behavioral; diff --git a/testsuite/synth/issue1090/tb_simple_ram.vhdl b/testsuite/synth/issue1090/tb_simple_ram.vhdl new file mode 100644 index 000000000..437c6543a --- /dev/null +++ b/testsuite/synth/issue1090/tb_simple_ram.vhdl @@ -0,0 +1,46 @@ +entity tb_simple_ram is +end tb_simple_ram; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_simple_ram is + signal raddr : std_logic_vector(5 downto 0); + signal rdat : std_logic_vector(31 downto 0); + signal en : std_logic; + signal waddr : std_logic_vector(5 downto 0); + signal wdat : std_logic_vector(31 downto 0); + signal we : std_logic_vector (3 downto 0); + signal clk : std_logic; +begin + dut: entity work.simple_ram + port map (clk => clk, + en => en, raddr => raddr, do => rdat, + we => we, waddr => waddr, di => wdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + en <= '1'; + raddr <= "000000"; + we <= "0000"; + waddr <= "000001"; + wdat <= x"00_00_00_01"; + pulse; + assert rdat = x"0000_0110" severity failure; + + raddr <= "000001"; + waddr <= "000010"; + wdat <= x"00_00_00_02"; + pulse; + assert rdat = x"0000_1ffc" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1090/testsuite.sh b/testsuite/synth/issue1090/testsuite.sh new file mode 100755 index 000000000..2e9bb84bb --- /dev/null +++ b/testsuite/synth/issue1090/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in simple_ram; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |