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authorTristan Gingold <tgingold@free.fr>2022-09-08 18:55:33 +0200
committerTristan Gingold <tgingold@free.fr>2022-09-08 18:55:33 +0200
commit3d50ceb1772ec529ed168579d3d0b5603df96493 (patch)
treee0909f14657f42c18b4c80d759c84591d10ea021 /testsuite/synth
parentde68a6b6b024d438f2242e2fddb7dd29cca59f3b (diff)
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testsuite/synth: add a test with uninitialized shared variable
Diffstat (limited to 'testsuite/synth')
-rw-r--r--testsuite/synth/synth109/ram10.vhdl38
-rw-r--r--testsuite/synth/synth109/tb_ram10.vhdl62
-rwxr-xr-xtestsuite/synth/synth109/testsuite.sh2
3 files changed, 101 insertions, 1 deletions
diff --git a/testsuite/synth/synth109/ram10.vhdl b/testsuite/synth/synth109/ram10.vhdl
new file mode 100644
index 000000000..77fd4c915
--- /dev/null
+++ b/testsuite/synth/synth109/ram10.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram10 is
+ generic (
+ WIDTHB : integer := 32;
+ SIZEB : integer := 64;
+ ADDRWIDTHB : integer := 6
+ );
+
+ port (
+ clkB : in std_logic;
+ enB : in std_logic;
+ weB : in std_logic;
+ addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
+ diB : in std_logic_vector(WIDTHB-1 downto 0);
+ doB : out std_logic_vector(WIDTHB-1 downto 0)
+ );
+
+end ram10;
+
+architecture behavioral of ram10 is
+ type ramType is array (0 to SIZEB-1) of std_logic_vector(WIDTHB-1 downto 0);
+ shared variable ram : ramType;
+begin
+ process (clkB)
+ begin
+ if rising_edge(clkB) then
+ if enB = '1' then
+ if weB = '1' then
+ ram(to_integer(unsigned(addrB))) := diB;
+ end if;
+ doB <= ram(to_integer(unsigned(addrB)));
+ end if;
+ end if;
+ end process;
+end behavioral;
diff --git a/testsuite/synth/synth109/tb_ram10.vhdl b/testsuite/synth/synth109/tb_ram10.vhdl
new file mode 100644
index 000000000..9d9e3c15c
--- /dev/null
+++ b/testsuite/synth/synth109/tb_ram10.vhdl
@@ -0,0 +1,62 @@
+entity tb_ram10 is
+end tb_ram10;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram10 is
+ signal clk : std_logic;
+ signal en : std_logic;
+ signal we : std_logic;
+ signal addr : std_logic_vector(5 downto 0);
+ signal rdat : std_logic_vector(31 downto 0);
+ signal wdat : std_logic_vector(31 downto 0);
+begin
+ dut: entity work.ram10
+ port map (clkB => clk, enB => en, weB => we, addrB => addr,
+ diB => wdat, doB => rdat);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en <= '1';
+ we <= '1';
+ addr <= b"00_0000";
+ wdat <= x"11_22_33_f0";
+ pulse;
+ assert rdat = x"11_22_33_f0" severity failure;
+
+ addr <= b"00_0001";
+ wdat <= x"11_22_33_f1";
+ pulse;
+ assert rdat = x"11_22_33_f1" severity failure;
+
+ -- Read.
+ we <= '0';
+ addr <= b"00_0000";
+ wdat <= x"ff_22_33_f1";
+ pulse;
+ assert rdat = x"11_22_33_f0" severity failure;
+
+ addr <= b"00_0001";
+ wdat <= x"ff_22_33_f1";
+ pulse;
+ assert rdat = x"11_22_33_f1" severity failure;
+
+ -- Disable.
+ en <= '0';
+ we <= '1';
+ addr <= b"00_0000";
+ wdat <= x"11_22_33_f0";
+ pulse;
+ assert rdat = x"11_22_33_f1" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/synth109/testsuite.sh b/testsuite/synth/synth109/testsuite.sh
index cc1803015..62e8026af 100755
--- a/testsuite/synth/synth109/testsuite.sh
+++ b/testsuite/synth/synth109/testsuite.sh
@@ -4,7 +4,7 @@
GHDL_STD_FLAGS="-fsynopsys"
-for t in ram1 ram2 ram4; do
+for t in ram1 ram10 ram2 ram4; do
synth_tb $t 2> $t.log
grep "found R" $t.log
done