testsuite/synth: add a test for #2204

6 files changed, 158 insertions, 0 deletions

diff --git a/testsuite/synth/issue2204/crash.vhdl b/testsuite/synth/issue2204/crash.vhdl
new file mode 100644
index 000000000..d0628c4ee
--- /dev/null
+++ b/testsuite/synth/issue2204/crash.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity crash is
+  port (
+    clk  : in  std_logic
+  );
+end entity crash;
+
+architecture rtl of crash is
+    signal index : std_logic := '0';
+begin
+
+    -- process (clk) is
+    --     begin
+    --       if rising_edge(clk) then
+-- >> This prints an error, but doesn't crash ghdl
+    --         index <= index = index'LAST_VALUE;
+    --       end if;
+    --     end process;
+
+  -- psl default clock is rising_edge(clk);
+
+  -- >> These crash after printing good errors, which still seems undesirable.
+  -- >> Remove the X to test them
+
+  -- psl crash_my_ghdl1 : cover
+  --    {index /= index'LAST_VALUE};
+  -- Xpsl crash_my_ghdl2 : cover
+  --    {index'EVENT};
+  -- Xpsl crash_my_ghdl3 : cover
+  --    {index'ACTIVE};
+
+
+end architecture rtl;
diff --git a/testsuite/synth/issue2204/crash2.vhdl b/testsuite/synth/issue2204/crash2.vhdl
new file mode 100644
index 000000000..8198403eb
--- /dev/null
+++ b/testsuite/synth/issue2204/crash2.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity crash is
+  port (
+    clk  : in  std_logic
+  );
+end entity crash;
+
+architecture rtl of crash is
+    signal index : std_logic := '0';
+begin
+
+    -- process (clk) is
+    --     begin
+    --       if rising_edge(clk) then
+-- >> This prints an error, but doesn't crash ghdl
+    --         index <= index = index'LAST_VALUE;
+    --       end if;
+    --     end process;
+
+  -- psl default clock is rising_edge(clk);
+
+  -- psl crash_my_ghdl2 : cover
+  --    {index'active or index'EVENT};
+
+
+end architecture rtl;
diff --git a/testsuite/synth/issue2204/crash3.vhdl b/testsuite/synth/issue2204/crash3.vhdl
new file mode 100644
index 000000000..491f15be8
--- /dev/null
+++ b/testsuite/synth/issue2204/crash3.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity crash is
+  port (
+    clk  : in  std_logic
+  );
+end entity crash;
+
+architecture rtl of crash is
+    signal index : std_logic := '0';
+begin
+
+    -- process (clk) is
+    --     begin
+    --       if rising_edge(clk) then
+-- >> This prints an error, but doesn't crash ghdl
+    --         index <= index = index'LAST_VALUE;
+    --       end if;
+    --     end process;
+
+  -- psl default clock is rising_edge(clk);
+
+  -- psl crash_my_ghdl2 : cover
+  --    {index'active and index'quiet};
+
+
+end architecture rtl;
diff --git a/testsuite/synth/issue2204/crash4.vhdl b/testsuite/synth/issue2204/crash4.vhdl
new file mode 100644
index 000000000..5513ef296
--- /dev/null
+++ b/testsuite/synth/issue2204/crash4.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity crash is
+  port (
+    clk  : in  std_logic
+  );
+end entity crash;
+
+architecture rtl of crash is
+    signal index : std_logic := '0';
+begin
+
+    -- process (clk) is
+    --     begin
+    --       if rising_edge(clk) then
+-- >> This prints an error, but doesn't crash ghdl
+    --         index <= index = index'LAST_VALUE;
+    --       end if;
+    --     end process;
+
+  -- psl default clock is rising_edge(clk);
+
+  -- psl crash_my_ghdl2 : cover
+  --    {index'active and (index'active and true)};
+
+
+end architecture rtl;
diff --git a/testsuite/synth/issue2204/crash5.vhdl b/testsuite/synth/issue2204/crash5.vhdl
new file mode 100644
index 000000000..21d8b7c64
--- /dev/null
+++ b/testsuite/synth/issue2204/crash5.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity crash is
+  port (
+    clk  : in  std_logic
+  );
+end entity crash;
+
+architecture rtl of crash is
+    signal index : std_logic := '0';
+begin
+
+    -- process (clk) is
+    --     begin
+    --       if rising_edge(clk) then
+-- >> This prints an error, but doesn't crash ghdl
+    --         index <= index = index'LAST_VALUE;
+    --       end if;
+    --     end process;
+
+  -- psl default clock is rising_edge(clk);
+
+  -- psl crash_my_ghdl2 : cover
+  --    {not index'active or index'event};
+
+
+end architecture rtl;
diff --git a/testsuite/synth/issue2204/testsuite.sh b/testsuite/synth/issue2204/testsuite.sh
new file mode 100755
index 000000000..fbfdffe1e
--- /dev/null
+++ b/testsuite/synth/issue2204/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure -fpsl crash.vhdl -e
+synth_failure -fpsl crash2.vhdl -e
+synth_failure -fpsl crash3.vhdl -e
+synth_failure -fpsl crash4.vhdl -e
+synth_failure -fpsl crash5.vhdl -e
+
+echo "Test successful"