initial support for reduce and/or (#900)

2 files changed, 25 insertions, 0 deletions

diff --git a/testsuite/synth/unary01/test.vhdl b/testsuite/synth/unary01/test.vhdl
new file mode 100644
index 000000000..a3d4271a9
--- /dev/null
+++ b/testsuite/synth/unary01/test.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+  port (a, b : in std_logic_vector(7 downto 0);
+        o, p : out std_logic);
+end test;
+
+architecture behav of test is
+begin
+  o <= or a;
+  p <= and b;
+end behav;
diff --git a/testsuite/synth/unary01/testsuite.sh b/testsuite/synth/unary01/testsuite.sh
new file mode 100755
index 000000000..3e8f8a082
--- /dev/null
+++ b/testsuite/synth/unary01/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth test.vhdl -e test > syn_test.vhdl
+analyze syn_test.vhdl
+clean
+
+echo "Test successful"