testsuite/synth: add testcase for tgingold/ghdlsynth-beta#36

3 files changed, 106 insertions, 0 deletions

diff --git a/testsuite/synth/synth36/bram.vhdl b/testsuite/synth/synth36/bram.vhdl
new file mode 100644
index 000000000..fcfb98b72
--- /dev/null
+++ b/testsuite/synth/synth36/bram.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity bram is
+  generic (
+    addr_width : integer := 9;
+    data_width : integer := 8
+  );
+  port (
+    clk      : in std_logic;
+    we       : in std_logic;
+    addr     : in std_logic_vector(addr_width-1 downto 0);
+    data_in  : in std_logic_vector(data_width-1 downto 0);
+    data_out : out std_logic_vector(data_width-1 downto 0)
+  );
+end bram;
+
+architecture rtl of bram is
+  type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
+  signal mem : mem_type;
+
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if we = '1' then
+        mem(to_integer(unsigned(addr))) <= data_in;
+      end if;
+    end if;
+  end process;
+  data_out <= mem(to_integer(unsigned(addr)));
+end rtl;
diff --git a/testsuite/synth/synth36/tb_bram.vhdl b/testsuite/synth/synth36/tb_bram.vhdl
new file mode 100644
index 000000000..c2e6d93a7
--- /dev/null
+++ b/testsuite/synth/synth36/tb_bram.vhdl
@@ -0,0 +1,57 @@
+entity tb_bram is
+end tb_bram;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_bram is
+  signal clk, we : std_logic;
+  signal addr : std_logic_vector (8 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+  signal din : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.bram
+    port map (clk => clk, we => we, addr => addr,
+              data_in => din, data_out => dout);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    we <= '1';
+    addr <= "000000001";
+    din <= x"f1";
+    pulse;
+
+    we <= '0';
+    pulse;
+    assert dout = x"f1" severity failure;
+
+    we <= '1';
+    addr <= "000000011";
+    din <= x"f3";
+    pulse;
+
+    we <= '1';
+    addr <= "111111111";
+    din <= x"ff";
+    pulse;
+
+    we <= '0';
+    addr <= "000000011";
+    pulse;
+    assert dout = x"f3" severity failure;
+
+    we <= '0';
+    addr <= "111111111";
+    pulse;
+    assert dout = x"ff" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth36/testsuite.sh b/testsuite/synth/synth36/testsuite.sh
new file mode 100755
index 000000000..7ea417f3f
--- /dev/null
+++ b/testsuite/synth/synth36/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in bram; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"