testsuite/synth: Add a test for ghdl/ghdl-yosys-plugin#154

2 files changed, 58 insertions, 0 deletions

diff --git a/testsuite/synth/synth154/keep.vhdl b/testsuite/synth/synth154/keep.vhdl
new file mode 100644
index 000000000..e8bb69132
--- /dev/null
+++ b/testsuite/synth/synth154/keep.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5 : out std_logic);
+end leds;
+
+architecture blink of leds is
+
+  signal clk_4hz: std_logic := '0';
+  constant gates: integer := 3 - 1;
+  signal max: integer := 3e6;
+  signal A: std_logic_vector(0 to gates) := ( others => '0');
+
+  attribute keep: boolean;
+  attribute keep of A: signal is true;
+
+  signal B: std_logic := '1';
+  signal C: std_logic := '1';
+  signal val: std_logic := '0';
+  signal data: std_logic := '0';
+
+begin
+  process (clk)
+    variable counter : unsigned (23 downto 0) := (others => '0');
+  begin
+    if rising_edge(clk) then
+      if counter >= max then
+        counter := x"000000";
+        clk_4hz <= not clk_4hz;
+      else
+        counter := counter + 1;
+      end if;
+    end if;
+  end process;
+
+GEN:
+    for i in 0 to gates generate
+        A(i) <= not A(gates - i);
+    end generate GEN;
+
+  led2 <= clk_4hz;
+  led3 <= clk_4hz;
+  led4 <= clk_4hz;
+  led5 <= clk_4hz;
+end;
diff --git a/testsuite/synth/synth154/testsuite.sh b/testsuite/synth/synth154/testsuite.sh
new file mode 100755
index 000000000..00c001dcb
--- /dev/null
+++ b/testsuite/synth/synth154/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_analyze keep
+grep -q "signal a : " syn_keep.vhdl
+clean
+
+echo "Test successful"