testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#128

3 files changed, 121 insertions, 0 deletions

diff --git a/testsuite/synth/synth128/tb_test.vhdl b/testsuite/synth/synth128/tb_test.vhdl
new file mode 100644
index 000000000..965e297da
--- /dev/null
+++ b/testsuite/synth/synth128/tb_test.vhdl
@@ -0,0 +1,73 @@
+entity tb_test is
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_test is
+  signal resb      : std_logic;
+  signal clk_FF    : std_logic;
+  signal ADD_FF    : unsigned(1 downto 0);
+  signal CONFIG    : std_logic;
+  signal D_FF      : std_logic;
+  signal WE        : std_logic;
+  signal EN_signal : std_logic;
+  signal a : std_logic;
+  signal b : std_logic;
+  signal c : std_logic;
+  signal z : std_logic;
+begin
+  dut: entity work.test
+    port map (
+      resb      => resb,
+      clk_FF    => clk_FF,
+      ADD_FF    => ADD_FF,
+      CONFIG    => CONFIG,
+      D_FF      => D_FF,
+      WE        => WE,
+      EN_signal => EN_signal);
+
+  process
+    procedure pulse is
+    begin
+      clk_ff <= '0';
+      wait for 1 ns;
+      clk_ff <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    resb <= '0';
+    config <= '1';
+    pulse;
+
+    assert en_signal = '0' severity failure;
+
+    resb <= '1';
+    d_ff <= '1';
+    add_ff <= "00";
+    we <= '1';
+    pulse;
+
+    assert en_signal = '1' severity failure;
+
+    d_ff <= '0';
+    add_ff <= "01";
+    pulse;
+
+    assert en_signal = '1' severity failure;
+
+    we <= '0';
+    add_ff <= "00";
+    pulse;
+
+    assert en_signal = '1' severity failure;
+
+    we <= '1';
+    pulse;
+
+    assert en_signal = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth128/test.vhdl b/testsuite/synth/synth128/test.vhdl
new file mode 100644
index 000000000..8c51dda9e
--- /dev/null
+++ b/testsuite/synth/synth128/test.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity test is
+  port (
+    resb: 		in std_logic;
+    clk_FF:		in std_logic;
+    ADD_FF: 		in unsigned(1 downto 0);
+    CONFIG: 		in std_logic;
+    D_FF: 		in std_logic;
+    WE:			in std_logic;
+    EN_signal:		out std_logic
+    );
+end test;
+
+architecture test_a of test is
+signal Q_FF: std_logic_vector(0 to 1);
+begin
+    process(resb, clk_FF)
+    begin
+	if resb = '0' then
+	    Q_FF <= "00";
+	elsif clk_FF'event and clk_FF = '1' then
+		if WE = '1' then
+			Q_FF(to_integer(ADD_FF)) <= D_FF;
+		end if;
+	end if;
+     end process;
+
+    process(CONFIG, Q_FF)
+    begin
+        if CONFIG = '1'  then
+            EN_signal <=  Q_FF(0);
+         else
+            EN_signal <= '0';
+         end if;
+      end process;
+end;
diff --git a/testsuite/synth/synth128/testsuite.sh b/testsuite/synth/synth128/testsuite.sh
new file mode 100755
index 000000000..6fc5761f5
--- /dev/null
+++ b/testsuite/synth/synth128/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in test; do
+    synth_tb $t
+done
+
+echo "Test successful"