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author | Tristan Gingold <tgingold@free.fr> | 2020-04-26 10:31:38 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-26 10:31:38 +0200 |
commit | c95cfdf958d9708d3e99c33aa76ba9e80c7ab32a (patch) | |
tree | 2362da44a34b1202f80a6750471360a97986e30f /testsuite/synth/synth109/ram1.vhdl | |
parent | bda14ed9ca901a0f5f7059e92a19fd88e0e1dab9 (diff) | |
download | ghdl-c95cfdf958d9708d3e99c33aa76ba9e80c7ab32a.tar.gz ghdl-c95cfdf958d9708d3e99c33aa76ba9e80c7ab32a.tar.bz2 ghdl-c95cfdf958d9708d3e99c33aa76ba9e80c7ab32a.zip |
testsuite/synth: add tests from ghdl/ghdl-yosys-plugin#109
Diffstat (limited to 'testsuite/synth/synth109/ram1.vhdl')
-rw-r--r-- | testsuite/synth/synth109/ram1.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/synth109/ram1.vhdl b/testsuite/synth/synth109/ram1.vhdl new file mode 100644 index 000000000..8fdbfbd5f --- /dev/null +++ b/testsuite/synth/synth109/ram1.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram1 is + generic ( + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkB : in std_logic; + enB : in std_logic; + weB : in std_logic; + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end ram1; + +architecture behavioral of ram1 is + type ramType is array (0 to SIZEB-1) of std_logic_vector(WIDTHB-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); +begin + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(to_integer(unsigned(addrB))) := diB; + end if; + doB <= ram(to_integer(unsigned(addrB))); + end if; + end if; + end process; +end behavioral; |