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authorTristan Gingold <tgingold@free.fr>2020-05-09 18:32:41 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-09 18:32:41 +0200
commit06202188e0e88c0096518415413c08bd0471644b (patch)
tree088ba5316602b01c9d2cedbfc6f6b37952b4b521 /testsuite/synth/synth104/testcase1.vhdl
parent894bbd7c174bafd59fbea3b3bd990ffdfbb685d2 (diff)
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testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#104
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diff --git a/testsuite/synth/synth104/testcase1.vhdl b/testsuite/synth/synth104/testcase1.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testcase1 is
+ port (
+ sel : in unsigned(1 downto 0);
+ det : out std_logic
+ );
+end testcase1;
+
+architecture behavior of testcase1 is
+begin
+ tc: process(sel)
+ begin
+ case to_integer(sel) is
+ when 0 to 1 =>
+ det <= '0';
+ when others =>
+ det <= '1';
+ end case;
+ end process;
+end behavior;