testsuite/synth: add a test for inout variable

3 files changed, 64 insertions, 0 deletions

diff --git a/testsuite/synth/subprg01/subprg01.vhdl b/testsuite/synth/subprg01/subprg01.vhdl
new file mode 100644
index 000000000..9a21cbb8c
--- /dev/null
+++ b/testsuite/synth/subprg01/subprg01.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subprg01 is
+  port (a : std_logic_vector (3 downto 0);
+        na : out std_logic_vector (3 downto 0));
+end subprg01;
+
+architecture behav of subprg01 is
+  procedure neg (v : inout std_logic_vector(3 downto 0)) is
+  begin
+    v := not v;
+  end neg;
+
+begin
+  process(A)
+    variable t : std_logic_vector(3 downto 0);
+  begin
+    t := a;
+    neg (t);
+    na <= t;
+  end process;
+end behav;
diff --git a/testsuite/synth/subprg01/tb_subprg01.vhdl b/testsuite/synth/subprg01/tb_subprg01.vhdl
new file mode 100644
index 000000000..de60ca324
--- /dev/null
+++ b/testsuite/synth/subprg01/tb_subprg01.vhdl
@@ -0,0 +1,25 @@
+entity tb_subprg01 is
+end tb_subprg01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_subprg01 is
+  signal a, na : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.subprg01
+    port map (a, na);
+
+  process
+  begin
+    a <= x"0";
+    wait for 1 ns;
+    assert na = x"f" severity failure;
+
+    a <= x"5";
+    wait for 1 ns;
+    assert na = x"a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/subprg01/testsuite.sh b/testsuite/synth/subprg01/testsuite.sh
new file mode 100755
index 000000000..82e200888
--- /dev/null
+++ b/testsuite/synth/subprg01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in subprg01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"