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author | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:54:09 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:55:53 +0200 |
commit | a18e1503a9896152268705aab21a6ee491756ff7 (patch) | |
tree | 7fd8a8fe8ca3cfca8687c6c2fe26e2224c712cf1 /testsuite/synth/snsuns01/tb_shrs.vhdl | |
parent | b46d4db8b112d40b056c102d65a64d08a00f4668 (diff) | |
download | ghdl-a18e1503a9896152268705aab21a6ee491756ff7.tar.gz ghdl-a18e1503a9896152268705aab21a6ee491756ff7.tar.bz2 ghdl-a18e1503a9896152268705aab21a6ee491756ff7.zip |
testsuite/synth: add tests for std_logic_unsigned and std_logic_signed.
Diffstat (limited to 'testsuite/synth/snsuns01/tb_shrs.vhdl')
-rw-r--r-- | testsuite/synth/snsuns01/tb_shrs.vhdl | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/testsuite/synth/snsuns01/tb_shrs.vhdl b/testsuite/synth/snsuns01/tb_shrs.vhdl new file mode 100644 index 000000000..2e0343350 --- /dev/null +++ b/testsuite/synth/snsuns01/tb_shrs.vhdl @@ -0,0 +1,56 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tb_shrs is +end; + +architecture behav of tb_shrs is + type sl_map_type is array (std_ulogic) of character; + constant sl_map : sl_map_type := "UX01ZWLH-"; + + function to_string(v : std_logic_vector) return string + is + alias av : std_logic_vector(1 to v'length) is v; + variable res : string (1 to v'length); + begin + for i in res'range loop + res (i) := sl_map (av (i)); + end loop; + return res; + end to_string; + + signal li : integer := 0; + signal ri : integer := 0; + + signal l3 : std_logic_vector (2 downto 0) := "000"; + signal r4 : std_logic_vector (3 downto 0) := "0000"; + signal shl_v3v4 : std_logic_vector (2 downto 0); + signal shr_v3v4 : std_logic_vector (2 downto 0); +begin + + dut: entity work.shrs + port map ( + l3 => l3, + r4 => r4, + shl_v3v4 => shl_v3v4, + shr_v3v4 => shr_v3v4); + + process + begin + for i in -4 to 3 loop + li <= i; + l3 <= conv_std_logic_vector (i, 3); + for j in 0 to 5 loop + r4 <= conv_std_logic_vector (j, 4); + ri <= j; + wait for 1 ns; + report "v3v4: " & integer'image(i) & " shl " & integer'image(j) & " = " + & to_string(shl_v3v4); + report "v3v4: " & integer'image(i) & " shr " & integer'image(j) & " = " + & to_string(shr_v3v4); + end loop; + end loop; + wait; + end process; +end behav; |