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authorTristan Gingold <tgingold@free.fr>2020-03-10 19:26:20 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-10 19:26:20 +0100
commitc7fc6185ae789e248c0752577ca44e6100616399 (patch)
tree9caa4eed4951ff38a523822073571d6c89ac4c91 /testsuite/synth/slice02/tb_slice02.vhdl
parent3ea034dfb17430430b49000f4d9e4d54032e4b3e (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/slice02/tb_slice02.vhdl')
-rw-r--r--testsuite/synth/slice02/tb_slice02.vhdl22
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/slice02/tb_slice02.vhdl b/testsuite/synth/slice02/tb_slice02.vhdl
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index 000000000..38cb294a3
--- /dev/null
+++ b/testsuite/synth/slice02/tb_slice02.vhdl
@@ -0,0 +1,22 @@
+entity tb_slice02 is
+end tb_slice02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_slice02 is
+ signal di : std_logic_vector (7 downto 0);
+ signal do : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.slice02
+ port map (di, do);
+
+ process
+ begin
+ di <= b"11_10_01_00";
+ wait for 1 ns;
+ assert do = b"10_11" severity error;
+
+ wait;
+ end process;
+end behav;