add synthesis support for logic operators on numeric types (#893)

* add logic operators on unsigned

* handle signed too

* handle unary not

1 files changed, 3 insertions, 3 deletions

diff --git a/testsuite/synth/psl01/hello.vhdl b/testsuite/synth/psl01/hello.vhdl
index 6f5e40735..6676b883a 100644
--- a/testsuite/synth/psl01/hello.vhdl
+++ b/testsuite/synth/psl01/hello.vhdl
@@ -22,8 +22,8 @@ begin
  end process;
  cnt <= val;
 
- --psl default clock is clk;
+ --psl default clock is rising_edge(clk);
  --psl restrict {rst; (not rst)[*]};
- --psl assert always val /= 5 or rst = '1';
- --psl assume always val < 50;
+ --psl assert always val /= 5 abort rst;
+ --psl assume always val < 10;
 end behav;