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authorPepijn de Vos <pepijndevos@gmail.com>2019-08-13 15:31:45 +0200
committertgingold <tgingold@users.noreply.github.com>2019-08-13 15:31:45 +0200
commit94f3226f10546f68d556b6567c5b0736456e7948 (patch)
treea4cac09e41722d187169a4de1d691762993ca38a /testsuite/synth/psl01
parent7e91b1419cde2a00c9288c02cda256a054ed6a3f (diff)
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Support for PSL assert and assume in synthesis (#892)
* initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
Diffstat (limited to 'testsuite/synth/psl01')
-rw-r--r--testsuite/synth/psl01/hello.vhdl3
1 files changed, 2 insertions, 1 deletions
diff --git a/testsuite/synth/psl01/hello.vhdl b/testsuite/synth/psl01/hello.vhdl
index fcf517757..6f5e40735 100644
--- a/testsuite/synth/psl01/hello.vhdl
+++ b/testsuite/synth/psl01/hello.vhdl
@@ -24,5 +24,6 @@ begin
--psl default clock is clk;
--psl restrict {rst; (not rst)[*]};
- assert val /= 5 or rst = '1' severity error;
+ --psl assert always val /= 5 or rst = '1';
+ --psl assume always val < 50;
end behav;