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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-13 22:43:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-13 22:43:47 +0200 |
| commit | de92555dc278dbb5799aaa386e1bd9b980ce0cbc (patch) | |
| tree | 32e26fc1c7d63f46987a00c22a6dd58b1157627b /testsuite/synth/psl01/testsuite.sh | |
| parent | 485b8f6b0260f5c0a72b8d6c42ad76c52fd889a1 (diff) | |
| download | ghdl-de92555dc278dbb5799aaa386e1bd9b980ce0cbc.tar.gz ghdl-de92555dc278dbb5799aaa386e1bd9b980ce0cbc.tar.bz2 ghdl-de92555dc278dbb5799aaa386e1bd9b980ce0cbc.zip | |
synth: extract edge for PSL clocks.
Diffstat (limited to 'testsuite/synth/psl01/testsuite.sh')
| -rwxr-xr-x | testsuite/synth/psl01/testsuite.sh | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh index e6d4050e6..4c43382b6 100755 --- a/testsuite/synth/psl01/testsuite.sh +++ b/testsuite/synth/psl01/testsuite.sh @@ -3,8 +3,11 @@ . ../../testenv.sh GHDL_STD_FLAGS=--std=08 -synth -fpsl hello.vhdl -e hello > syn_hello.vhdl -analyze syn_hello.vhdl + +for f in restrict1 assume1 assert1; do + synth -fpsl $f.vhdl -e $f > syn_$f.vhdl + analyze syn_$f.vhdl +done clean echo "Test successful" |