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author | tmeissner <programming@goodcleanfun.de> | 2021-10-14 12:33:03 +0200 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2021-10-14 22:16:18 +0200 |
commit | 164d834a13dc992f541d0bed50bcaacf3958249c (patch) | |
tree | 87637037e6199682d930d5c621fdee8e428d1943 /testsuite/synth/psl01/sequence0.vhdl | |
parent | 6b363405d67d29350f84a0c13e0b6c4297257271 (diff) | |
download | ghdl-164d834a13dc992f541d0bed50bcaacf3958249c.tar.gz ghdl-164d834a13dc992f541d0bed50bcaacf3958249c.tar.bz2 ghdl-164d834a13dc992f541d0bed50bcaacf3958249c.zip |
Add test for PSL declarations in inline PSL
Diffstat (limited to 'testsuite/synth/psl01/sequence0.vhdl')
-rw-r--r-- | testsuite/synth/psl01/sequence0.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/psl01/sequence0.vhdl b/testsuite/synth/psl01/sequence0.vhdl new file mode 100644 index 000000000..67edc7723 --- /dev/null +++ b/testsuite/synth/psl01/sequence0.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sequence0 is + port (clk, rst: std_logic; + cnt : out unsigned(3 downto 0)); +end sequence0; + +architecture behav of sequence0 is + signal val : unsigned (3 downto 0); + default clock is rising_edge(clk); +begin + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + val <= (others => '0'); + else + val <= val + 1; + end if; + end if; + end process; + cnt <= val; + + sequence seq is {val = 8; val = 9}; + + assert always seq |=> {val = 10} abort rst; + + cover seq; + +end behav; |