synth: add tests for partial assignment.

1 files changed, 13 insertions, 0 deletions

diff --git a/testsuite/synth/output01/output01.vhdl b/testsuite/synth/output01/output01.vhdl
new file mode 100644
index 000000000..1700bb53d
--- /dev/null
+++ b/testsuite/synth/output01/output01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity output01 is
+  port (i : std_logic;
+        o : out std_logic_vector (1 downto 0));
+end output01;
+
+architecture behav of output01 is
+begin
+  o (0) <= i;
+  o (1) <= not i;
+end behav;