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author | Tristan Gingold <tgingold@free.fr> | 2021-11-11 05:17:31 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-11 05:17:31 +0100 |
commit | 5df8168bf4eee942315144ddb4cb6f72357a889f (patch) | |
tree | 6dd9a29c207a78fcb3c0bf364d9cc3542532d660 /testsuite/synth/oper02/tb_urot01.vhdl | |
parent | fcd7769e2347e37681bade9f51dc9e8a09fe612b (diff) | |
download | ghdl-5df8168bf4eee942315144ddb4cb6f72357a889f.tar.gz ghdl-5df8168bf4eee942315144ddb4cb6f72357a889f.tar.bz2 ghdl-5df8168bf4eee942315144ddb4cb6f72357a889f.zip |
testsuite/synth: add tests for rol/ror. For #1909
Diffstat (limited to 'testsuite/synth/oper02/tb_urot01.vhdl')
-rw-r--r-- | testsuite/synth/oper02/tb_urot01.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/oper02/tb_urot01.vhdl b/testsuite/synth/oper02/tb_urot01.vhdl new file mode 100644 index 000000000..2875bbe96 --- /dev/null +++ b/testsuite/synth/oper02/tb_urot01.vhdl @@ -0,0 +1,25 @@ +entity tb_urot01 is +end tb_urot01; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_urot01 is + signal v : unsigned(7 downto 0); + signal ro : unsigned(7 downto 0); + signal lo : unsigned(7 downto 0); +begin + dut: entity work.urot01 + port map (v, ro, lo); + + process + begin + v <= x"14"; + wait for 1 ns; + assert ro = x"0a" severity failure; + assert lo = x"28" severity failure; + + wait; + end process; +end behav; |