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authorTristan Gingold <tgingold@free.fr>2021-10-18 07:48:33 +0200
committerTristan Gingold <tgingold@free.fr>2021-10-18 07:55:02 +0200
commit260be4a7519dd69c508dd1d013f07269921dad7f (patch)
treeb8d92ae6fb008fb325ee67736211c98eac028e5a /testsuite/synth/oper02/tb_uns02.vhdl
parent7e36182602ff1a2c43723240860029ad8ae007b5 (diff)
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testsuite/synth: add a test for #1896
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-rw-r--r--testsuite/synth/oper02/tb_uns02.vhdl20
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diff --git a/testsuite/synth/oper02/tb_uns02.vhdl b/testsuite/synth/oper02/tb_uns02.vhdl
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+entity tb_uns02 is
+end tb_uns02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uns02 is
+ signal r : boolean;
+begin
+ cmp01_1: entity work.uns02
+ port map (r);
+
+ process
+ begin
+ wait for 1 ns;
+ assert r severity failure;
+
+ wait;
+ end process;
+end behav;