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authorTristan Gingold <tgingold@free.fr>2020-03-10 20:42:02 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-10 20:42:02 +0100
commitbe40560c399be55a0145feec81a07fa89bf6704f (patch)
tree745c592bcd93eb9733e55a4dcced4e630518bf87 /testsuite/synth/oper02/tb_min01.vhdl
parent63e0082aa92df57f99347ace07b706b51b7fd4c9 (diff)
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testsuite/synth: add tests for previous commit.
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-rw-r--r--testsuite/synth/oper02/tb_min01.vhdl26
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diff --git a/testsuite/synth/oper02/tb_min01.vhdl b/testsuite/synth/oper02/tb_min01.vhdl
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+entity tb_min01 is
+end tb_min01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_min01 is
+ signal l, r : natural;
+ signal res : natural;
+begin
+ min01_1: entity work.min01
+ port map (
+ a => l,
+ b => r,
+ o => res);
+
+ process
+ begin
+ l <= 12;
+ r <= 15;
+ wait for 1 ns;
+ assert res = 12 severity failure;
+
+ wait;
+ end process;
+end behav;