synth: add tests for uns/uns comparisons.

3 files changed, 102 insertions, 0 deletions

diff --git a/testsuite/synth/oper01/cmp01.vhdl b/testsuite/synth/oper01/cmp01.vhdl
new file mode 100644
index 000000000..2452bf8da
--- /dev/null
+++ b/testsuite/synth/oper01/cmp01.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity cmp01 is
+  port (l : std_logic_vector(3 downto 0);
+        r :  std_logic_vector(3 downto 0);
+        eq : out std_logic;
+        ne : out std_logic;
+        lt : out std_logic;
+        le : out std_logic;
+        ge : out std_logic;
+        gt : out std_logic);
+end cmp01;
+
+architecture behav of cmp01 is
+begin
+  eq <= '1' when unsigned(l) = unsigned(r) else '0';
+  ne <= '1' when unsigned(l) /= unsigned(r) else '0';
+  lt <= '1' when unsigned(l) < unsigned(r) else '0';
+  le <= '1' when unsigned(l) <= unsigned(r) else '0';
+  gt <= '1' when unsigned(l) > unsigned(r) else '0';
+  ge <= '1' when unsigned(l) >= unsigned(r) else '0';
+end behav;
diff --git a/testsuite/synth/oper01/tb_cmp01.vhdl b/testsuite/synth/oper01/tb_cmp01.vhdl
new file mode 100644
index 000000000..31c613503
--- /dev/null
+++ b/testsuite/synth/oper01/tb_cmp01.vhdl
@@ -0,0 +1,62 @@
+entity tb_cmp01 is
+end tb_cmp01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_cmp01 is
+  signal l  : std_logic_vector(3 downto 0);
+  signal r  : std_logic_vector(3 downto 0);
+  signal eq : std_logic;
+  signal ne : std_logic;
+  signal lt : std_logic;
+  signal le : std_logic;
+  signal ge : std_logic;
+  signal gt : std_logic;
+begin
+  cmp01_1: entity work.cmp01
+    port map (
+      l  => l,
+      r  => r,
+      eq => eq,
+      ne => ne,
+      lt => lt,
+      le => le,
+      ge => ge,
+      gt => gt);
+
+  process
+  begin
+    l <= x"5";
+    r <= x"7";
+    wait for 1 ns;
+    assert eq = '0' severity failure;
+    assert ne = '1' severity failure;
+    assert lt = '1' severity failure;
+    assert le = '1' severity failure;
+    assert ge = '0' severity failure;
+    assert gt = '0' severity failure;
+
+    l <= x"a";
+    r <= x"7";
+    wait for 1 ns;
+    assert eq = '0' severity failure;
+    assert ne = '1' severity failure;
+    assert lt = '0' severity failure;
+    assert le = '0' severity failure;
+    assert ge = '1' severity failure;
+    assert gt = '1' severity failure;
+
+    l <= x"9";
+    r <= x"9";
+    wait for 1 ns;
+    assert eq = '1' severity failure;
+    assert ne = '0' severity failure;
+    assert lt = '0' severity failure;
+    assert le = '1' severity failure;
+    assert ge = '1' severity failure;
+    assert gt = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/oper01/testsuite.sh b/testsuite/synth/oper01/testsuite.sh
new file mode 100755
index 000000000..19c995cd1
--- /dev/null
+++ b/testsuite/synth/oper01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in cmp01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"