testsuite/synth: add more tests for memory

5 files changed, 217 insertions, 0 deletions

diff --git a/testsuite/synth/mem03/ram01.vhdl b/testsuite/synth/mem03/ram01.vhdl
new file mode 100644
index 000000000..195e27a1d
--- /dev/null
+++ b/testsuite/synth/mem03/ram01.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram01 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        wen : std_logic;
+        clk : std_logic);
+end ram01;
+
+architecture behav of ram01 is
+  type memdat is record
+    d1 : std_logic_vector(7 downto 0);
+  end record;
+
+  type memtype is array(0 to 15) of memdat;
+begin
+  process (clk)
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      if wen = '1' then
+        mem (to_integer(unsigned (waddr))).d1 := wdat;
+      end if;
+
+      --  The read port is synchronous
+      rdat <= mem (to_integer(unsigned (raddr))).d1;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem03/ram02.vhdl b/testsuite/synth/mem03/ram02.vhdl
new file mode 100644
index 000000000..99ed68bde
--- /dev/null
+++ b/testsuite/synth/mem03/ram02.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram02 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        wen : std_logic;
+        clk : std_logic);
+end ram02;
+
+architecture behav of ram02 is
+  type memdat is record
+    d1 : std_logic_vector(7 downto 0);
+  end record;
+
+  type memtype is array(0 to 15) of memdat;
+  signal rdat2 : std_logic_vector(7 downto 0);
+begin
+  process (clk)
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      if wen = '1' then
+        mem (to_integer(unsigned (waddr))).d1 := wdat;
+      end if;
+    end if;
+    rdat2 <= mem (to_integer(unsigned (raddr))).d1;
+  end process;
+
+  --  The read port is not synchronous
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      rdat <= rdat2;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem03/tb_ram01.vhdl b/testsuite/synth/mem03/tb_ram01.vhdl
new file mode 100644
index 000000000..d4a552b59
--- /dev/null
+++ b/testsuite/synth/mem03/tb_ram01.vhdl
@@ -0,0 +1,67 @@
+entity tb_ram01 is
+end tb_ram01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram01 is
+  signal raddr, waddr : std_logic_vector(3 downto 0) := (others => '0');
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ram01
+    port map (raddr => raddr, rdat => rdat,
+              waddr => waddr, wdat => wdat,
+              wen => wen, clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    --  [0] := x03, 1
+    waddr <= "0000";
+    wdat <= x"03";
+    wen <= '1';
+    pulse;
+
+    --  [1] := x41
+    waddr <= "0001";
+    wdat <= x"41";
+    raddr <= "0000";
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    --  [4] := x07
+    --  In case of conflict, read output is what is written.
+    waddr <= "0100";
+    wdat <= x"07";
+    raddr <= "0100";
+    wait for 1 ns;
+    pulse;
+    assert rdat = x"07" severity failure;
+
+    --  Not en.
+    waddr <= "0000";
+    wen <= '0';
+    raddr <= "0000";
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    --  [4] := x23
+    wen <= '1';
+    waddr <= "0100";
+    wdat <= x"23";
+    raddr <= "0001";
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem03/tb_ram02.vhdl b/testsuite/synth/mem03/tb_ram02.vhdl
new file mode 100644
index 000000000..8c92a680d
--- /dev/null
+++ b/testsuite/synth/mem03/tb_ram02.vhdl
@@ -0,0 +1,66 @@
+entity tb_ram02 is
+end tb_ram02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram02 is
+  signal raddr, waddr : std_logic_vector(3 downto 0) := (others => '0');
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ram02
+    port map (raddr => raddr, rdat => rdat,
+              waddr => waddr, wdat => wdat,
+              wen => wen, clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    --  [0] := x03, 1
+    waddr <= "0000";
+    wdat <= x"03";
+    wen <= '1';
+    pulse;
+
+    --  [1] := x41
+    waddr <= "0001";
+    wdat <= x"41";
+    raddr <= "0000";
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    --  [4] := x07
+    waddr <= "0100";
+    wdat <= x"07";
+    raddr <= "0001";
+    wait for 1 ns;
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    --  Not en.
+    waddr <= "0000";
+    wen <= '0';
+    raddr <= "0000";
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    --  [4] := x23
+    wen <= '1';
+    waddr <= "0100";
+    wdat <= x"23";
+    raddr <= "0001";
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem03/testsuite.sh b/testsuite/synth/mem03/testsuite.sh
new file mode 100755
index 000000000..7a876ae85
--- /dev/null
+++ b/testsuite/synth/mem03/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ram01 ram02; do
+    synth_tb $t 2> $t.log
+done
+
+clean
+
+echo "Test successful"