testsuite/synth: add mem02

3 files changed, 84 insertions, 0 deletions

diff --git a/testsuite/synth/mem02/dpram1.vhdl b/testsuite/synth/mem02/dpram1.vhdl
new file mode 100644
index 000000000..7801e6c0f
--- /dev/null
+++ b/testsuite/synth/mem02/dpram1.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram1 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram1;
+
+architecture behav of dpram1 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+    variable ra : natural;
+    variable wa : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram1.vhdl b/testsuite/synth/mem02/tb_dpram1.vhdl
new file mode 100644
index 000000000..f7644fbfe
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram1.vhdl
@@ -0,0 +1,40 @@
+entity tb_dpram1 is
+end tb_dpram1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram1 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram1
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    pulse;
+
+    raddr <= "0001";
+    waddr <= "0010";
+    wdat <= x"02";
+    pulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
new file mode 100755
index 000000000..ace30ab35
--- /dev/null
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in dpram1; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"