testsuite/synth: add a test for 'to' direction.

3 files changed, 64 insertions, 1 deletions

diff --git a/testsuite/synth/mem02/ram6.vhdl b/testsuite/synth/mem02/ram6.vhdl
new file mode 100644
index 000000000..621e7cc27
--- /dev/null
+++ b/testsuite/synth/mem02/ram6.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram6 is
+  port (val : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (2 downto 0);
+        wdat : std_logic;
+        clk : std_logic);
+end ram6;
+
+architecture behav of ram6 is
+  signal mem : std_logic_vector(0 to 7);
+begin
+  process (clk)
+    variable ra : natural;
+    variable wa : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (waddr));
+      mem(ra) <= wdat;
+    end if;
+  end process;
+  val <= mem;
+end behav;
diff --git a/testsuite/synth/mem02/tb_ram6.vhdl b/testsuite/synth/mem02/tb_ram6.vhdl
new file mode 100644
index 000000000..bf93b0be5
--- /dev/null
+++ b/testsuite/synth/mem02/tb_ram6.vhdl
@@ -0,0 +1,38 @@
+entity tb_ram6 is
+end tb_ram6;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram6 is
+  signal val : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(2 downto 0);
+  signal wdat : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ram6
+    port map (waddr => waddr, wdat => wdat, val => val,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    waddr <= "000";
+    wdat <= '0';
+    pulse;
+
+    waddr <= "001";
+    wdat <= '1';
+    pulse;
+
+    assert (val and x"c0") = x"40" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index d212c22e3..bd199178b 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dpram1 ram3 ram4; do
+for t in dpram1 ram3 ram4 ram6; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean